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    Recording A Communication Pattern and Replaying Messages in a Parallel Computing System
    21.
    发明申请
    Recording A Communication Pattern and Replaying Messages in a Parallel Computing System 失效
    在并行计算系统中记录通信模式和回放消息

    公开(公告)号：US20110010471A1

    公开(公告)日：2011-01-13

    申请号：US12500715

    申请日：2009-07-10

    申请人： Philip Heidelberger ,  Sameer Kumar

    发明人： Philip Heidelberger ,  Sameer Kumar

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories. The local instances of the global message passing application are configured to record, in the injection FIFO in the corresponding one of the memories, message descriptors associated with messages of an arbitrary communication pattern in an iteration of an executing application program. The local instances of the global message passing application are configured to replay the message descriptors during a subsequent iteration of the executing application program.

    摘要翻译： 并行计算机系统包括多个计算节点。 每个计算节点包括耦合到至少一个处理器和至少一个存储器的至少一个处理器，至少一个存储器和直接存储器地址引擎。 该系统还包括互连多个计算节点的网络。 该网络运行全球消息传递应用程序，用于跨网络执行通信。 全局消息传递应用的本地实例在每个计算节点处操作，以独立于在另一个计算节点处执行的处理操作来执行本地处理操作。 直接存储器地址引擎被配置为通过描述在对应的一个存储器中的注入FIFO的注入FIFO元数据与全局消息传递应用的本地实例进行交互。 全局消息传递应用程序的本地实例被配置为在执行的应用程序的迭代中在对应的一个存储器中的注入FIFO中记录与任意通信模式的消息相关联的消息描述符。 全局消息传递应用程序的本地实例被配置为在执行的应用程序的后续迭代期间重播消息描述符。

    Method of fabrication of on-chip heat pipes and ancillary heat transfer components
    22.
    发明授权
    Method of fabrication of on-chip heat pipes and ancillary heat transfer components 有权
    片上热管和辅助传热部件的制造方法

    公开(公告)号：US07781884B2

    公开(公告)日：2010-08-24

    申请号：US11863477

    申请日：2007-09-28

    申请人： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    发明人： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    IPC分类号： H01L23/34

    CPC分类号： H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

    摘要翻译： 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

    Direct Memory Access Transfer Completion Notification
    24.
    发明申请
    Direct Memory Access Transfer Completion Notification 失效
    直接内存访问传输完成通知

    公开(公告)号：US20080307121A1

    公开(公告)日：2008-12-11

    申请号：US11758167

    申请日：2007-06-05

    申请人： Dong Chen ,  Mark E. Giampapa ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker ,  Burkhard D. Steinmacher-Burow ,  Pavlos Vranas

    发明人： Dong Chen ,  Mark E. Giampapa ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker ,  Burkhard D. Steinmacher-Burow ,  Pavlos Vranas

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

    摘要翻译： 提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。 实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器 依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

    Replenishing Data Descriptors in a DMA Injection FIFO Buffer
    26.
    发明申请
    Replenishing Data Descriptors in a DMA Injection FIFO Buffer 失效
    在DMA注入FIFO缓冲区中补充数据描述符

    公开(公告)号：US20100268852A1

    公开(公告)日：2010-10-21

    申请号：US11755501

    申请日：2007-05-30

    申请人： Charles J Archer ,  Michael A. Blocksome ,  Bob R. Cernohous ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker

    发明人： Charles J Archer ,  Michael A. Blocksome ,  Bob R. Cernohous ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： Methods, apparatus, and products are disclosed for replenishing data descriptors in a Direct Memory Access (‘DMA’) injection first-in-first-out (‘FIFO’) buffer that include: determining, by a messaging module on an origin compute node, whether a number of data descriptors in a DMA injection FIFO buffer exceeds a predetermined threshold, each data descriptor specifying an application message for transmission to a target compute node; queuing, by the messaging module, a plurality of new data descriptors in a pending descriptor queue if the number of the data descriptors in the DMA injection FIFO buffer exceeds the predetermined threshold; establishing, by the messaging module, interrupt criteria that specify when to replenish the injection FIFO buffer with the plurality of new data descriptors in the pending descriptor queue; and injecting, by the messaging module, the plurality of new data descriptors into the injection FIFO buffer in dependence upon the interrupt criteria.

    摘要翻译： 公开了用于在直接存储器访问（“DMA”）注入先进先出（'FIFO'）缓冲器中补充数据描述符的方法，装置和产品，其包括：由原始计算节点 无论DMA注入FIFO缓冲器中的多个数据描述符是否超过预定阈值，每个数据描述符指定用于传输到目标计算节点的应用消息; 如果DMA注入FIFO缓冲器中的数据描述符的数量超过预定阈值，则由消息接发模块排队等待描述符队列中的多个新数据描述符; 由所述消息传递模块建立中断标准，所述中断标准指定何时用所述待处理描述符队列中的所述多个新数据描述符补充所述注入FIFO缓冲器; 以及根据所述中断标准，由所述消息收发模块将所述多个新数据描述符注入到所述注入FIFO缓冲器中。

    Elevated track for support of signal lines on a printed circuit board assembly
    28.
    发明授权
    Elevated track for support of signal lines on a printed circuit board assembly 有权
    用于支撑印刷电路板组件上的信号线的高架轨道

    公开(公告)号：US07301102B1

    公开(公告)日：2007-11-27

    申请号：US10716268

    申请日：2003-11-17

    申请人： Sriram Gopalaratnam ,  Sameer Kumar Gupta

    发明人： Sriram Gopalaratnam ,  Sameer Kumar Gupta

    IPC分类号： H05K1/00

    CPC分类号： H05K3/222 ,  H05K3/301 ,  H05K2201/10287 ,  H05K2201/10409 ,  H05K2201/10598

    摘要： A printed circuit board assembly utilizing an elevated track to support signal lines between components is disclosed. The track rests on a plurality of vertical supports, placed amid the components, such that the signal lines can be routed after the components are configured on the board. The vertical supports can be installed at grounding holes already present on the printed circuit board assembly. The track is sufficiently rigid to support bundles of signal lines over long spans between vertical supports. The track can be constructed of the same material as the board, to provide the same ESD and conductivity characteristics as the board, as well as ensure that the track does not contribute to the EMI signature of the board.

    摘要翻译： 公开了一种使用高架轨道支撑组件之间的信号线的印刷电路板组件。 轨道位于多个垂直支撑件上，放置在组件中，使得信号线可以在组件配置在板上之后进行路由。 垂直支撑件可以安装在已经存在于印刷电路板组件上的接地孔中。 该轨道具有足够的刚性以在垂直支撑之间的长跨度上支撑信号线束。 轨道可以由与板相同的材料构成，以提供与板相同的ESD和导电特性，以及确保轨道不会对板的EMI特征有贡献。

    Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect
    29.
    发明授权
    Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect 有权

    公开(公告)号：US07115467B2

    公开(公告)日：2006-10-03

    申请号：US10903712

    申请日：2004-07-30

    申请人： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

    发明人： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/75

    摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).