公开(公告)号：US5874347A

公开(公告)日：1999-02-23

申请号：US688283

申请日：1996-07-29

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/76202

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

Abstract translation: 公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜 以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。 由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

公开(公告)号：US5696007A

公开(公告)日：1997-12-09

申请号：US729840

申请日：1996-10-15

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/70 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/072

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.

Abstract translation: 本发明涉及一种能够使元件小型化的超自对准异质结双极晶体管的制造方法，通过采用选择性集电体外延生长和多选择性基极电极简化其工艺步骤，而不使用用于隔离元件之间的沟槽， 从而提高其性能，其包括以下步骤：在衬底的顶部上顺次形成第一氧化膜，导电薄膜和第二氧化膜; 图案化第二氧化膜和导电薄膜以形成预备间隔物; 去除第一氧化膜的暴露部分，并选择性地生长集电体层; 氧化所述集电体层以形成热氧化膜，并除去所述预备间隔物; 在所述第二氧化膜上分别沉积多晶硅并形成硅氧化膜和多晶硅间隔物和所述预备间隔物的去除部分; 暴露基底薄膜，间隔物和集电极层以形成SiGe / Si层; 在SiGe / Si层上形成基极; 暴露第一氧化膜的一部分并形成第三氧化膜; 暴露SiGe / Si层的表面并在蚀刻部分的侧面上形成氧化间隔物，然后自发对准发射极和发射极; 并执行金属布线处理。

公开(公告)号：US5496745A

公开(公告)日：1996-03-05

申请号：US358825

申请日：1994-12-19

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L29/66287 ,  H01L21/76224 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072

Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.

Abstract translation: 公开了使用增强的沟槽隔离来改善其集成和性能的双极晶体管的制造，其包括以下步骤：使用沟槽形成掩模将对应于沟槽的部分依次蚀刻到掩埋集电极的预定深度，以形成 沟; 将隔离绝缘层填充到沟槽中; 将隔离绝缘层抛光直到氧化硅层的表面; 在隔离绝缘层和氧化硅层上依次形成第二绝缘层; 除去形成在除了由沟槽限定的有源区域之外的非活性区域上的第一多晶硅层和第一绝缘层; 对形成在非活性区域上的集电体层进行热氧化以形成热氧化物层; 去除所述第二绝缘层并顺序地形成第三多晶硅，第三绝缘层和第二氮化物层; 蚀刻形成在所述第一绝缘层的一部分上的层以在所述有源区中形成开口; 在所述开口的两个边缘上形成第一侧壁并移除所述第一绝缘层; 在去除所述第一绝缘层的区域上形成本征基极以使所述本征基极与自对准的外部基极电连接; 在所述第一侧壁的两侧上形成第二侧壁; 并在本征基底上形成发射极层。

公开(公告)号：US09034850B2

公开(公告)日：2015-05-19

申请号：US13511065

申请日：2010-11-19

Applicant: Seon Mi Kim ,  Min Hee Lee ,  Jae Sun Kim ,  Hoe Chul Jung ,  So Young Lee ,  Soo Min Lee ,  Eun Jeong Kim ,  Eui Sun Park ,  Sung Hoon Park ,  Bong Yong Lee ,  Key An Um

Inventor： Seon Mi Kim ,  Min Hee Lee ,  Jae Sun Kim ,  Hoe Chul Jung ,  So Young Lee ,  Soo Min Lee ,  Eun Jeong Kim ,  Eui Sun Park ,  Sung Hoon Park ,  Bong Yong Lee ,  Key An Um

IPC: A01N57/00 ,  C07D239/545 ,  A61K31/506 ,  C07D239/46 ,  C07D401/04 ,  C07D403/04 ,  C07D405/14 ,  C07D213/74 ,  C07D253/075 ,  C07D401/12 ,  C07D401/14 ,  C07D403/06 ,  C07D403/12 ,  C07D405/12 ,  C07D409/12 ,  C07D409/14 ,  C07D413/12 ,  C07D417/12 ,  C07D487/04 ,  C07D491/048 ,  C07F9/6558

CPC classification number: C07D239/545 ,  A61K31/506 ,  C07D213/74 ,  C07D239/46 ,  C07D253/075 ,  C07D401/04 ,  C07D401/12 ,  C07D401/14 ,  C07D403/04 ,  C07D403/06 ,  C07D403/12 ,  C07D405/12 ,  C07D405/14 ,  C07D409/12 ,  C07D409/14 ,  C07D413/12 ,  C07D417/12 ,  C07D487/04 ,  C07D491/048 ,  C07F9/65583 ,  C07F9/65586

Abstract: Disclosed are compounds useful as gonadotrophin-releasing hormone (“GnRH”) receptor antagonist.

Abstract translation: 公开了可用作促性腺激素释放激素（“GnRH”）受体拮抗剂的化合物。

公开(公告)号：US20100190968A1

公开(公告)日：2010-07-29

申请号：US12446523

申请日：2006-10-24

Applicant: Bong Cheol Kim ,  Wonrack Choi ,  Soo Min Lee ,  Se Jun Yun ,  Chang-Kyun Han ,  Guang-Jin Im ,  Wie-Jong Kwak

Inventor： Bong Cheol Kim ,  Wonrack Choi ,  Soo Min Lee ,  Se Jun Yun ,  Chang-Kyun Han ,  Guang-Jin Im ,  Wie-Jong Kwak

IPC: C07H15/256

CPC classification number: A61K31/015

Abstract: The present invention relates to the use of oleanane-type triterpene saponin compounds, which are effective for improving memory and learning ability, as an effective ingredient of drugs for the treatment and prevention of dementia and mild cognitive impairment and health foods for the improvement of brain functions including cognitive function.

Abstract translation: 本发明涉及作为治疗和预防痴呆和轻度认知障碍的药物的有效成分和用于改善脑的健康食品的有利于提高记忆力和学习能力的油酸型三萜皂苷化合物的用途 功能包括认知功能。

公开(公告)号：US07645688B2

公开(公告)日：2010-01-12

申请号：US11790329

申请日：2007-04-25

Applicant: Soo Min Lee ,  Masayoshi Koike ,  Sung Hwan Jang ,  Hyo Won Suh

Inventor： Soo Min Lee ,  Masayoshi Koike ,  Sung Hwan Jang ,  Hyo Won Suh

IPC: H01L21/20 ,  H01L21/36

CPC classification number: C30B25/02 ,  C30B25/183 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02472 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02609

Abstract: A method of growing a non-polar m-plane nitride semiconductor. A (11-23) plane sapphire substrate is prepared, and a non-polar (10-10) nitride semiconductor is grown on the sapphire substrate. The present invention can also be applied to a method for manufacturing other m-plane hexagonal semiconductors.

Abstract translation: 一种生长非极性m面氮化物半导体的方法。 制备（11-23）平面蓝宝石衬底，在蓝宝石衬底上生长非极性（10-10）氮化物半导体。 本发明也可以应用于制造其它m面六边形半导体的方法。

公开(公告)号：US07468103B2

公开(公告)日：2008-12-23

申请号：US10837709

申请日：2004-05-04

Applicant: Soo Min Lee ,  Hun Joo Hahm ,  Young Ho Park

Inventor： Soo Min Lee ,  Hun Joo Hahm ,  Young Ho Park

IPC: C30B25/18

CPC classification number: C30B29/40 ,  C30B25/02 ,  C30B25/20 ,  Y10S117/915

Abstract: Disclosed herein is a method of manufacturing a gallium nitride-based (AlxInyGa(1−x−y)N, where 0≦x≦1, 0≦y≦1, 0≦x+y≦1) single crystal substrate. The method comprises the steps of preparing a ZnO substrate, primarily growing a gallium nitride-based single crystal layer, and secondarily growing an additional gallium nitride-based single crystal layer on the primarily grown gallium nitride-based single crystal layer while removing the ZnO substrate by etching the underside of the ZnO substrate.

Abstract translation: 本文公开了一种制造氮化镓基（Al x In y Ga（1-xy）N）的方法，其中0 <= x <=1,0,0≤y≤1,0<= x + y <= 1）单晶 基质。 该方法包括以下步骤：制备ZnO衬底，主要生长氮化镓基单晶层，然后在主要生长的氮化镓基单晶层上再次生长附加的氮化镓基单晶层，同时去除ZnO衬底 通过蚀刻ZnO衬底的下侧。

公开(公告)号：US20060148186A1

公开(公告)日：2006-07-06

申请号：US11220020

申请日：2005-09-06

Applicant: Soo Min Lee ,  Masayoshi Koike ,  Kyeong Ik Min ,  Cheol Kyu Kim ,  Sung Hwan Jang ,  Min Ho Kim

Inventor： Soo Min Lee ,  Masayoshi Koike ,  Kyeong Ik Min ,  Cheol Kyu Kim ,  Sung Hwan Jang ,  Min Ho Kim

IPC: H01L21/336

CPC classification number: C30B29/406 ,  C30B29/64 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02664

Abstract: A method and apparatus for manufacturing a nitride based single crystal substrate. The method includes placing a preliminary substrate on a susceptor installed in a reaction chamber; growing a nitride single crystal layer on the preliminary substrate; and irradiating a laser beam to separate the nitride single crystal layer from the preliminary substrate under the condition that the preliminary substrate is placed in the reaction chamber.

Abstract translation: 一种用于制造氮化物基单晶衬底的方法和装置。 该方法包括将初步衬底放置在安装在反应室中的基座上; 在初始衬底上生长氮化物单晶层; 并且在预备衬底放置在反应室中的条件下照射激光束以将氮化物单晶层与预备衬底分离。

公开(公告)号：US06893889B2

公开(公告)日：2005-05-17

申请号：US10735615

申请日：2003-12-16

Applicant: Young Ho Park ,  Hun Joo Hahm ,  Soo Min Lee

Inventor： Young Ho Park ,  Hun Joo Hahm ,  Soo Min Lee

IPC: H01L33/06 ,  H01L33/20 ,  H01L33/32 ,  H01L33/42 ,  H01L33/44 ,  H01L29/06 ,  H01L31/0336 ,  H01L31/109

CPC classification number: H01L33/42 ,  H01L33/38

Abstract: A method of manufacturing a gallium nitride-based semiconductor light emitting device, includes sequentially forming, over a substrate, a first conductivity type clad layer, an active layer, and a second conductivity type clad layer, forming a transparent electrode over the second conductivity type clad layer, forming a photoresist film on the transparent electrode such that the transparent electrode is exposed at a predetermined region, removing respective portions of the transparent electrode, second conductivity type clad layer, and active layer corresponding to the predetermined region, thereby partially exposing the first conductivity type clad layer, removing the photoresist film, and forming first and second bonding electrodes on predetermined portions of the transparent electrode and second conductivity type clad layer, respectively.

Abstract translation: 一种制造氮化镓基半导体发光器件的方法，包括在衬底上顺序地形成第一导电型覆盖层，有源层和第二导电型覆盖层，在第二导电类型上形成透明电极 在所述透明电极上形成光致抗蚀剂膜，使得所述透明电极在预定区域露出，除去与所述预定区域对应的所述透明电极，第二导电型覆盖层和有源层的各部分，从而部分地曝光 第一导电型覆盖层，去除光致抗蚀剂膜，以及分别在透明电极和第二导电型覆盖层的预定部分上形成第一和第二接合电极。

公开(公告)号：US06552374B2

公开(公告)日：2003-04-22

申请号：US09765499

申请日：2001-01-17

Applicant: Tae-Hyeon Han ,  Byung Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho

Inventor： Tae-Hyeon Han ,  Byung Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho

IPC: H01L31072

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: Disclosed are a method for forming a base layer by epitaxial growth technology of a heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of depositing an insulation film containing silicon nitride on a substrate and removing a part of the insulation film to define a collector area; growing a first semiconductor in the collector area by selective epitaxial growth method to form the collector protruded over the insulation film in the form of a mushroom; forming an oxide film containing silicon dioxide on a surface of the collector protruded over the silicon nitride; selectively growing a second polycrystalline semiconductor material on only the nitride insulation film at the same height as the protruded portion of the collector to form a first base semiconductor electrode; removing an upper surface of the oxide film to expose the collector; and growing a second semiconductor containing silicon-germanium on the second polycrystalline semiconductor and the collector of the first semiconductor to form a second base semiconductor electrode on the first base semiconductor electrode and the base on the collector, thereby preventing a current leakage and a loading effect.