公开(公告)号：US07528450B2

公开(公告)日：2009-05-05

申请号：US11889766

申请日：2007-08-16

申请人： Tomonori Aoyama

发明人： Tomonori Aoyama

IPC分类号： H01L29/78

CPC分类号： H01L21/28052 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823835 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film is made up of a silicon oxide film and a hafnium silicon oxynitride film. The n-type gate electrode is made up of an n-type silicon film and a nickel silicide film, and the p-type gate electrode is made up of a nickel silicide film. The hafnium silicon oxynitride films are not formed on the sidewalls of the gate electrodes.

摘要翻译： 在硅衬底的器件区域周围形成元件隔离绝缘膜。 器件区域形成n型扩散层区域，p型扩散层区域，p型延伸区域，n型延伸区域，p型源极/漏极区域，n型源极/ 漏极区域和硅化镍膜。 每个栅极电介质膜由氧化硅膜和铪硅氮氧化物膜构成。 n型栅电极由n型硅膜和硅化镍膜构成，p型栅电极由硅化镍膜构成。 在栅电极的侧壁上不形成铪硅氮氧化物膜。

公开(公告)号：US20080054365A1

公开(公告)日：2008-03-06

申请号：US11889766

申请日：2007-08-16

申请人： Tomonori Aoyama

发明人： Tomonori Aoyama

IPC分类号： H01L27/092

CPC分类号： H01L21/28052 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823835 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film is made up of a silicon oxide film and a hafnium silicon oxynitride film. The n-type gate electrode is made up of an n-type silicon film and a nickel silicide film, and the p-type gate electrode is made up of a nickel silicide film. The hafnium silicon oxynitride films are not formed on the sidewalls of the gate electrodes.

摘要翻译： 在硅衬底的器件区域周围形成元件隔离绝缘膜。 器件区域形成n型扩散层区域，p型扩散层区域，p型延伸区域，n型延伸区域，p型源极/漏极区域，n型源极/ 漏极区域和硅化镍膜。 每个栅极电介质膜由氧化硅膜和铪硅氮氧化物膜构成。 n型栅电极由n型硅膜和硅化镍膜构成，p型栅电极由硅化镍膜构成。 在栅电极的侧壁上不形成铪硅氮氧化物膜。

公开(公告)号：US20070190768A1

公开(公告)日：2007-08-16

申请号：US11699396

申请日：2007-01-30

申请人： Motoyuki Sato ,  Tomonori Aoyama

发明人： Motoyuki Sato ,  Tomonori Aoyama

IPC分类号： H01L21/4763

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L29/4975 ,  H01L29/517

摘要： A method of manufacturing a semiconductor device, includes forming a gate insulating film on a semiconductor substrate, and forming a gate electrode on the gate insulting film, wherein forming the gate insulating film includes forming a metal silicate film, and a silicon source used for forming the metal silicate film includes at least one of a first hydrocarbon silicon compound obtained by replacing at least one of hydrogen atoms in monosilane with an alkyl group, a second hydrocarbon silicon compound obtained by replacing at least one of hydrogen atoms in disilane with an alkyl group, and a third hydrocarbon silicon compound obtained by replacing at least one of hydrogen atoms in trisilane with an alkyl group.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成栅极绝缘膜，并且在栅极绝缘膜上形成栅极电极，其中形成栅极绝缘膜包括形成金属硅酸盐膜和用于形成的硅源 金属硅酸盐膜包括通过用烷基取代甲硅烷中的至少一个氢原子得到的第一烃硅化合物，通过用烷基取代乙硅烷中的至少一个氢原子而获得的第二烃硅化合物中的至少一种 和通过用烷基取代丙硅烷中的至少一个氢原子得到的第三烃硅化合物。

公开(公告)号：US20070167243A1

公开(公告)日：2007-07-19

申请号：US10589896

申请日：2005-03-01

申请人： Tsutomu Kawakatsu ,  Takahiro Ogura ,  Naoto Shibata ,  Shouichi Nakano ,  Tomonori Aoyama

发明人： Tsutomu Kawakatsu ,  Takahiro Ogura ,  Naoto Shibata ,  Shouichi Nakano ,  Tomonori Aoyama

IPC分类号： F16D3/26

CPC分类号： F16D3/2055

摘要： An annular member is installed on a circular cylinder section of a trunnion, and a roller member, in the inner periphery of which a needle bearing is held, is installed on the circular cylinder section. The needle bearing is held between a flange section formed on one end of the roller member and the annular member installed on the trunnion with a predetermined gap between them. Further, a gap (X) between the needle bearing and the annular member is set to satisfy the following relationship. X>R/2·(1/cos θ max−1) where R: Radius of rotation of the center of the roller member relative to the center axis of an outer member. θ max: Maximum inclination angle of an inner member.

摘要翻译： 环形构件安装在耳轴的圆筒部分上，并且在圆筒部分上安装有在其内周上保持有滚针轴承的滚轮构件。 滚针轴承保持在形成在滚子构件的一端的凸缘部分和安装在耳轴上的环形构件之间，其间具有预定的间隙。 此外，滚针轴承和环形构件之间的间隙（X）设定为满足以下关系。 X> R / 2（1 /cosθmax-1）其中R：辊构件的中心相对于外部构件的中心轴线的旋转半径。 θmax：内部构件的最大倾斜角度。

公开(公告)号：US20050181607A1

公开(公告)日：2005-08-18

申请号：US11094308

申请日：2005-03-31

申请人： Tomonori Aoyama

发明人： Tomonori Aoyama

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device includes a first insulating film on a silicon substrate and a second insulating film on the first insulating film. The first insulating film is a silicon oxide film having a thickness of 1 nm or less and a suboxide content of 30% or less. The second insulating film is a high dielectric constant insulating film.

摘要翻译： 半导体器件包括硅衬底上的第一绝缘膜和第一绝缘膜上的第二绝缘膜。 第一绝缘膜是厚度为1nm以下，低氧化物含量为30％以下的氧化硅膜。 第二绝缘膜是高介电常数绝缘膜。

公开(公告)号：US06794286B2

公开(公告)日：2004-09-21

申请号：US09558053

申请日：2000-04-26

申请人： Hisako Aoyama ,  Kyoichi Suguro ,  Hiromi Niiyama ,  Hitoshi Tamura ,  Hisataka Hayashi ,  Tomonori Aoyama ,  Gaku Minamihaba ,  Tadashi Iijima

发明人： Hisako Aoyama ,  Kyoichi Suguro ,  Hiromi Niiyama ,  Hitoshi Tamura ,  Hisataka Hayashi ,  Tomonori Aoyama ,  Gaku Minamihaba ,  Tadashi Iijima

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.

摘要翻译： 半导体器件包括其中形成半导体元件的半导体衬底，形成在半导体衬底上的层间绝缘膜，通过等离子体氮化形成在层间绝缘膜上的绝缘阻挡层，用于防止构成布线层的金属的扩散 形成在绝缘阻挡层上的用于防止金属扩散的导电阻挡层，以及由金属形成的布线层在导电阻挡层上。 布线层的底部由导电阻挡层和绝缘阻挡层保护。 因此，可以可靠地防止构成布线层的金属的扩散。

公开(公告)号：US5929473A

公开(公告)日：1999-07-27

申请号：US842646

申请日：1997-04-15

申请人： Kazuya Nishihori ,  Yoshiaki Kitaura ,  Yoshikazu Tanabe ,  Tomonori Aoyama ,  Kyoichi Suguro ,  Kumi Okuwada ,  Shuichi Komatsu ,  Kazuhide Abe

发明人： Kazuya Nishihori ,  Yoshiaki Kitaura ,  Yoshikazu Tanabe ,  Tomonori Aoyama ,  Kyoichi Suguro ,  Kumi Okuwada ,  Shuichi Komatsu ,  Kazuhide Abe

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/095 ,  H01L29/92 ,  H01L29/812

CPC分类号： H01L27/0629 ,  H01L27/0605 ,  H01L27/10852 ,  H01L28/40

摘要： An SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 nm) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

摘要翻译： 在GaAs衬底上依次排列有SiO 2膜和第一布线层。 在第一布线层上形成电容器。 电容器包括从下侧依次具有由Ti层，Mo层和Pt层构成的多层结构的下电极。 电容器还包括由钛酸锶制成的电介质膜。 电容器还包括从下侧依次具有由WNx层（120nm）和W层（300nm）构成的多层结构的上部电极。 与电介质膜接触的上电极的表面由氮化钨层限定。

公开(公告)号：US07858524B2

公开(公告)日：2010-12-28

申请号：US11600794

申请日：2006-11-17

申请人： Tomonori Aoyama

发明人： Tomonori Aoyama

IPC分类号： H01L21/441

CPC分类号： H01L21/823835 ,  H01L29/1033

摘要： A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.

摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体基板上的栅极绝缘膜; 形成在栅极绝缘膜上的n型MISFET的硅化物栅电极; 以及形成在栅极绝缘膜上并且具有比n型MISFET的硅化物栅电极的厚度小的p型MISFET的硅化物栅电极，p型MISFET的硅化物栅电极的比例为 金属含量高于n型MISFET的硅化物栅电极。

公开(公告)号：US20100055854A1

公开(公告)日：2010-03-04

申请号：US12585555

申请日：2009-09-17

申请人： Takuya Kobayashi ,  Katsuyuki Sekine ,  Tomonori Aoyama ,  Hiroshi Tomita

发明人： Takuya Kobayashi ,  Katsuyuki Sekine ,  Tomonori Aoyama ,  Hiroshi Tomita

IPC分类号： H01L21/8234

CPC分类号： H01L21/02148 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/31645 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/6656

摘要： A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上的层间电介质膜中形成沟槽，沟槽到达半导体衬底并具有由氮化硅膜制成的侧壁; 在200摄氏度至260摄氏度的温度范围内沉积由HfSiO膜制成的栅极绝缘膜，使得HfSiO膜沉积在暴露于沟槽底表面的半导体衬底上，而不沉积HfSiO 膜上的氮化硅膜; 并用金属制成的栅电极填充沟槽。

公开(公告)号：US20090114996A1

公开(公告)日：2009-05-07

申请号：US12261770

申请日：2008-10-30

申请人： Seiji Inumiya ,  Takuya Kobayashi ,  Tomonori Aoyama

发明人： Seiji Inumiya ,  Takuya Kobayashi ,  Tomonori Aoyama

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/02148 ,  H01L21/02156 ,  H01L21/02161 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645

摘要： A semiconductor device includes a substrate having first and second regions on a surface thereof, a first conductivity type first MISFET formed in the first region and a second conductivity type second MISFET formed in the second region. The first MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate and a first insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film and which has a first element forming electric dipoles that reduce a threshold voltage of the first MISFET and the second MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate, and a second insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film formed on the surface of the substrate and which has a second element forming electric dipoles in a direction opposite to that in the first MISFET.

摘要翻译： 半导体器件包括在其表面上具有第一和第二区域的衬底，在第一区域中形成的第一导电类型的第一MISFET和形成在第二区域中的第二导电类型的第二MISFET。 第一MISFET包括在基板的表面上形成的氧化硅膜或氮氧化硅膜，以及形成为与氧化硅膜或氮氧化硅膜接触形成的第一元件的第一绝缘膜，其具有形成电偶极子的第一元件， 降低第一MISFET的阈值电压，并且第二MISFET包括在衬底的表面上形成的氧化硅膜或氧氮化硅膜，以及形成为与氧化硅膜或氮氧化硅膜接触的第二绝缘膜 形成在基板的表面上，并且具有在与第一MISFET中的方向相反的方向上形成电偶极子的第二元件。