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公开(公告)号：US09059207B2
公开(公告)日：2015-06-16
申请号：US13613747
申请日：2012-09-13
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1054 , H01L21/02529 , H01L21/02532 , H01L21/306 , H01L21/31144 , H01L21/324 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/785 , H01L29/78687
摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
摘要翻译： 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层 的多层应变通道部分。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。
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22.发明申请公开(公告)号：US20140038369A1
公开(公告)日：2014-02-06
申请号：US13565838
申请日：2012-08-03
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/845 , H01L27/1211
摘要： Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins.
摘要翻译： 各种实施例包括形成半导体结构的方法。 在一个实施例中，一种方法包括：提供包括衬底和覆盖衬底的一组鳍片的前体结构; 在翅片组中的翅片之间形成虚拟外延; 掩蔽该组散热片中的第一组散热片和在一组翅片中的第一组翅片之间的虚设外延; 去除所述虚拟外延以暴露第二组散热片; 在暴露的翅片之间形成第一原位掺杂外延; 掩蔽该组散热片中的第二组翅片和在该组翅片中的第二组翅片之间的原位掺杂的外延; 揭开第一组翅片; 去除第一组翅片之间的虚拟外延层以暴露第一组翅片; 以及在所述暴露的鳍之间形成第二原位掺杂的外延。
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23.发明申请CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE 审中-公开具有应变源/漏区的CMOS器件和低接触电阻公开(公告)号：US20140001561A1
公开(公告)日：2014-01-02
申请号：US13534522
申请日：2012-06-27
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A CMOS device structure and method of manufacturing the same are provided. The CMOS device structure includes a substrate having a first region and a second region. The CMOS device structure further includes a first gate formed in the first region overlying a first channel region in the substrate. The CMOS device structure further includes a first pair of source/drain regions formed in the first region on either side of the first channel region. Each region of the pair of source/drain regions has a substantially V-shaped concave top surface.
摘要翻译： 提供了一种CMOS器件结构及其制造方法。 CMOS器件结构包括具有第一区域和第二区域的衬底。 CMOS器件结构还包括形成在覆盖衬底中的第一沟道区域的第一区域中的第一栅极。 CMOS器件结构还包括形成在第一沟道区两侧的第一区域中的第一对源/漏区。 一对源极/漏极区域中的每个区域具有大致V形的凹顶表面。
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公开(公告)号：US20130307076A1
公开(公告)日：2013-11-21
申请号：US13472605
申请日：2012-05-16
IPC分类号： H01L27/12 , H01L21/8234
CPC分类号： H01L21/845 , H01L27/0802 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.
摘要翻译： 公开了一种鳍式电阻器和制造方法。 散热片电阻器包括以具有外延区域的交替图案的线性图案布置的多个散热片。 退火将掺杂剂从外延区域扩散到鳍片中。 触头连接到端点外延区域，以允许电阻器连接到更复杂的集成电路。
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25.发明申请TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION 失效具有改进的SIGMA形状嵌入式压力器的晶体管和形成方法公开(公告)号：US20130285123A1
公开(公告)日：2013-10-31
申请号：US13457980
申请日：2012-04-27
IPC分类号： H01L29/78 , H01L21/336 , H01L21/20
CPC分类号： H01L21/02609 , H01L21/265 , H01L21/28026 , H01L21/30608 , H01L21/3065 , H01L21/308 , H01L21/3086 , H01L29/165 , H01L29/66431 , H01L29/6653 , H01L29/66575 , H01L29/66636 , H01L29/7848
摘要： A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
摘要翻译： 具有西格玛通道侧壁和垂直隔离侧壁的半导体晶体管器件中的嵌入式应力源的方法和结构。 嵌入的应力器结构由第一蚀刻制成，以在具有栅极和第一和第二间隔物的衬底中形成凹陷。 去除第二间隔物，并且第二蚀刻在通道侧壁上的凹部中形成台阶。 各向异性蚀刻在凹槽的通道侧壁中产生刻面。 小面相遇时，形成顶点。 顶点的深度由第二蚀刻深度（阶梯深度）决定。 顶点的横向位置由第一间隔件的厚度决定。 在凹部中形成具有与衬底不同的晶格间距的半导体材料，以实现嵌入的应力器结构。
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公开(公告)号：US20130249006A1
公开(公告)日：2013-09-26
申请号：US13424787
申请日：2012-03-20
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823431 , H01L21/823475 , H01L29/41791 , H01L29/66628 , H01L29/7834
摘要： A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.
摘要翻译： 在平面场效应晶体管的平面源极/漏极区域或与鳍状场效应晶体管的沟道区域相邻的半导体鳍片的一部分的表面上形成下部凸起的源极/漏极区域。 形成并平坦化至少一个接触层介电材料层，并且在该至少一个接触层电介质材料层中形成延伸到下凸起源/漏区的接触通孔。 上凸起的源/漏区形成在下凸起的源/漏区的顶表面上。 在接触通孔内形成金属半导体合金部分和接触通孔结构。 上部隆起源极/漏极区域的形成被限制在接触通孔的底部，从而通过未被接触的源极/漏极区域中的任何额外的凸起结构来防止寄生电容的形成和增加。
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公开(公告)号：US20130200459A1
公开(公告)日：2013-08-08
申请号：US13364850
申请日：2012-02-02
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/02529 , H01L21/02532 , H01L21/306 , H01L21/31144 , H01L21/324 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/785 , H01L29/78687
摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
摘要翻译： 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，具有由多层应变通道分离的厚度小于10nm的源极和漏极部分。SOI层的多层应变通道包括第一层 其具有存在于SOI衬底的掩埋电介质层上的第一晶格尺寸，以及与多层应变通道部分的第一层直接接触的第二晶格尺寸的第二层。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。
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公开(公告)号：US20130161694A1
公开(公告)日：2013-06-27
申请号：US13607875
申请日：2012-09-10
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L29/78 , H01L27/12
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译： 一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。 在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。 在第一半导体层的蚀刻表面上外延形成第二半导体层。 栅极结构直接形成在第二半导体层上。 源极区域和漏极区域形成在栅极结构的相对侧上。
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公开(公告)号：US08962434B2
公开(公告)日：2015-02-24
申请号：US13545224
申请日：2012-07-10
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02576 , H01L21/02579 , H01L21/28008 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L29/167 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/7834 , H01L29/7848
摘要： A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
摘要翻译： 一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。
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公开(公告)号：US08828831B2
公开(公告)日：2014-09-09
申请号：US13355691
申请日：2012-01-23
IPC分类号： H01L29/772 , H01L29/417 , H01L21/8238
CPC分类号： H01L29/0603 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/092 , H01L29/165 , H01L29/41725 , H01L29/66628 , H01L29/772 , H01L29/78
摘要： Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.
摘要翻译： 公开了一种半导体制品，其包括半导体衬底; 栅极结构具有与栅极结构的导电材料相邻的间隔物，其中间隔物的角被刻面以在刻面间隔物和半导体衬底之间产生刻面空间; 以及与栅极结构相邻的升高的源极/漏极，所述升高的源极/漏极填充所述刻面空间并具有平行于所述半导体衬底的表面。 还公开了制造半导体制品的方法。
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