Abstract:
In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract:
An SOC includes a secure processor and an always-on component. The always-on component may remain powered even during times that other parts of the SOC are powered off. Particularly, the secure processor and related circuitry may be powered off, while various state for the secure processor may be stored in memory in an encrypted form. Certain state may be stored in the always-on component. When the secure processor is powered on again, the secure processor may check for the state in the always-on component. If the state is found, the secure processor may retrieve the state and use the state to access the encrypted memory state.
Abstract:
In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract:
In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract:
Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.
Abstract:
A portable communication device (PCD) can automatically switch into different operating modes of an asymmetric communication protocol (such as USB) depending on the type of accessory connected. For example, the accessory can signal whether the PCD should operate in a first mode or a second mode using a hardware indicator such as identification resistor across two pins of a multi-pin connector and/or a software indicator such as a command protocol. The PCD can detect the accessory's signal and switch to the operating mode requested by the accessory.
Abstract:
In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.
Abstract:
In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract:
In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract:
Methods and apparatus for managing connections be multiple internal integrated circuits (ICs) of for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter. Chip™ (HSIC) in are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved dining, synchronization, and power consumption.