公开(公告)号：US08953372B2

公开(公告)日：2015-02-10

申请号：US13936622

申请日：2013-07-08

Applicant: Apple Inc.

Inventor： Avraham Poza Meir ,  Barak Baum ,  Naftali Sommer

IPC: G11C11/34 ,  G06F11/10 ,  G11C7/06 ,  G11C8/08 ,  G11C11/4091 ,  G11C11/56 ,  G11C13/00 ,  G11C16/26 ,  G11C16/34 ,  G11C27/00 ,  G11C8/12 ,  G11C29/00

CPC classification number: G06F11/1008 ,  G11C7/06 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4091 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/26 ,  G11C16/349 ,  G11C27/005 ,  G11C29/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5641

Abstract: A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.

Abstract translation: 用于数据存储的方法包括通过将相应的存储值写入组中的存储器单元来将数据存储在一组模拟存储器单元中。 使用以第一感测时间感测存储器单元的第一读出操作读取组中的一个或多个存储器单元。 使用第二读出操作来读取组中的至少一个存储器单元，该第二读出操作以比第一感测时间长的第二感测时间感测存储器单元。 基于第一和第二读出操作的读出结果重建存储在存储单元组中的数据。

公开(公告)号：US20140325310A1

公开(公告)日：2014-10-30

申请号：US13908041

申请日：2013-06-03

Applicant: Apple Inc.

Inventor： Micha Anholt ,  Eyal Gurgi ,  Barak Baum ,  Moshe Neerman ,  Moti Teitel

IPC: G06F11/10

CPC classification number: G11C29/021 ,  G06F11/1072 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/00 ,  G11C29/028 ,  G11C29/42

Abstract: A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page.

Abstract translation: 一种在包括多个模拟存储器单元的存储器中的方法包括将一组存储器单元分成公共部分和至少第一和第二专用部分。 每个专用部分对应于用于读取要存储在组中的数据页的读取阈值。 要存储在组中的数据通过公共部分和第一专用部分的并集，并且在公共部分和第二专用部分的联合之间共同平衡，以创建平衡页面，使得对于每个相应的读取阈值 相同数量的存储器单元将被编程为假设由读取阈值分开的编程电平。 平衡页面存储到公共和专用部分，并且基于检测平衡页面的读出结果中的数据值之间的不平衡来调整读取阈值。

公开(公告)号：US08773905B1

公开(公告)日：2014-07-08

申请号：US13786792

申请日：2013-03-06

Applicant: Apple Inc.

Inventor： Alex Radinski ,  Barak Baum ,  Eyal Gurgi ,  Micha Anholt ,  Ronen Dar ,  Tomer Ish-Shalom ,  Yael Shur

IPC: G11C16/26 ,  G11C16/34 ,  G11C27/00 ,  G11C16/04

CPC classification number: G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5641

Abstract: A method includes performing a read operation that reads data from a group of analog memory cells using at least one read threshold, to produce readout results. A detection is made that the read threshold is set in a restricted range that causes the readout results not to reflect the read threshold. The data is reproduced from the group of the memory cells while compensating for the read threshold that is set in the restricted range.

Abstract translation: 一种方法包括执行使用至少一个读取阈值从一组模拟存储器单元读取数据的读取操作，以产生读出结果。 检测到读取阈值被设置在导致读出结果不反映读取阈值的限制范围内。 在对限制范围内设定的读取阈值进行补偿的同时，从存储单元组再现数据。

公开(公告)号：US20200005874A1

公开(公告)日：2020-01-02

申请号：US16202130

申请日：2018-11-28

Applicant: Apple Inc.

Inventor： Assaf Shappir ,  Barak Baum ,  Itay Sagron ,  Roman Guy ,  Guy Ben-Yehuda ,  Stas Mouler

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C29/12 ,  G06F11/10

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.

公开(公告)号：US20180358103A1

公开(公告)日：2018-12-13

申请号：US15992229

申请日：2018-05-30

Applicant: Apple Inc.

Inventor： Yael Shur ,  Assaf Shappir ,  Barak Baum ,  Roman Guy ,  Michael Tsohar

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3418

Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

公开(公告)号：US10146460B1

公开(公告)日：2018-12-04

申请号：US15716703

申请日：2017-09-27

Applicant: Apple Inc.

Inventor： Barak Baum ,  Barak Sagiv ,  Einav Yogev ,  Eyal Gurgi ,  Ariel Landau

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F11/002 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/108 ,  G06F11/3058 ,  G11C7/04 ,  G11C11/5642

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

公开(公告)号：US10008278B1

公开(公告)日：2018-06-26

申请号：US15619494

申请日：2017-06-11

Applicant: Apple Inc.

Inventor： Yael Shur ,  Assaf Shappir ,  Barak Baum ,  Roman Guy ,  Michael Tsohar

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3418

Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

公开(公告)号：US09672925B2

公开(公告)日：2017-06-06

申请号：US15066020

申请日：2016-03-10

Applicant: Apple Inc.

Inventor： Arik Rizel ,  Avraham Poza Meir ,  Yael Shur ,  Eyal Gurgi ,  Barak Baum

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L27/11568

CPC classification number: G11C16/24 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11568 ,  H01L29/42328

Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.

公开(公告)号：US09390809B1

公开(公告)日：2016-07-12

申请号：US14617961

申请日：2015-02-10

Applicant: APPLE INC.

Inventor： Yael Shur ,  Avraham Poza Meir ,  Barak Baum ,  Eyal Gurgi

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/70 ,  G11C2029/1202

Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

Abstract translation: 一种方法包括定义用于应用于存储块的字线（WL）和位线（BL）的正常电压配置以及不同于正常电压配置的异常电压配置，以应用于WL和BL 当在存储器块中的至少两个WL之间找到字线到字线（WL-WL）短路时，存储块。 如果在存储块中没有发现WL-WL短路，则通过施加正常电压配置在存储块中执行数据存储操作。 如果在存储器块中发现WL-WL短路，则通过应用异常电压配置在存储块中执行数据存储操作。

公开(公告)号：US20140331106A1

公开(公告)日：2014-11-06

申请号：US13874995

申请日：2013-05-01

Applicant: APPLE INC.

Inventor： Barak Baum ,  Tomer Ish-Shalom ,  Micha Anholt ,  Eyal Gurgi ,  Yoav Kasorla

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  G11C7/14 ,  G11C11/5621 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

Abstract: A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count.

Abstract translation: 一种方法包括在包括两个或多个存储器单元的存储器中，存储可由多个检验方程表示的纠错码（ECC）的代码字，使得代码字的第一部分被存储在 第一存储单元和码字的第二部分被存储在第二存储单元中。 识别仅对属于存储在第一存储器单元中的第一部分的代码字位操作的检验方程的子集。 从第一存储器单元检索代码字的第一部分，并且对所检索的代码字的第一部分不满足的所识别的子集中的检验方程的计数进行评估。 根据评估计数来设定用于从第一存储器单元读出的一个或多个读出参数。