公开(公告)号：US20210043515A1

公开(公告)日：2021-02-11

申请号：US16533590

申请日：2019-08-06

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Zavier Zai Yeong Tan ,  James S. Papanu

IPC: H01L21/82 ,  H01L21/3065 ,  H01L21/308 ,  B23K26/064 ,  B23K26/067

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a spatially multi-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US09972575B2

公开(公告)日：2018-05-15

申请号：US15060224

申请日：2016-03-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC: H01L21/78 ,  H01L23/544 ,  B23K26/0622 ,  B23K10/00 ,  A47G19/22 ,  B65D47/24 ,  B65D47/32

CPC classification number: H01L23/544 ,  A47G19/22 ,  A47G19/2272 ,  B23K10/003 ,  B23K26/0624 ,  B65D47/244 ,  B65D47/32 ,  H01L21/78 ,  H01L2223/5446

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US09852997B2

公开(公告)日：2017-12-26

申请号：US15081296

申请日：2016-03-25

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/78 ,  B23K26/359 ,  B23K26/064 ,  B23K26/364

CPC classification number: B23K26/064 ,  B23K26/0006 ,  B23K26/0624 ,  B23K26/355 ,  B23K26/359 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/40 ,  B23K2101/42 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US09343366B2

公开(公告)日：2016-05-17

申请号：US14543747

申请日：2014-11-17

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/3065 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12041 ,  H01L2224/11 ,  H01L2924/00

Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.

Abstract translation: 描述了具有背面焊料凸块的晶片的混合激光划片和等离子体蚀刻切割工艺的方法。 例如，在其前侧具有集成电路的半导体晶片的切割方法和背面的金属凸块的相应阵列包括在半导体晶片的背面施加切割带，该切割带覆盖金属凸块的阵列 。 该方法还包括在半导体晶片的正面上形成掩模，该掩模覆盖集成电路。 该方法还涉及通过激光划线工艺在半导体晶片的正面上形成刻划线，在掩模中形成划线并在集成电路之间。 该方法还包括通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，掩模在等离子体蚀刻期间保护集成电路。

公开(公告)号：US11764061B2

公开(公告)日：2023-09-19

申请号：US17529130

申请日：2021-11-17

Applicant: Applied Materials, Inc.

Inventor： Wenguang Li ,  James S. Papanu

IPC: H01L21/027 ,  H01L21/3065 ,  H01L21/78 ,  H01L21/308 ,  H01L21/822

CPC classification number: H01L21/0275 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/30655 ,  H01L21/78 ,  H01L21/822

Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.

公开(公告)号：US20230187215A1

公开(公告)日：2023-06-15

申请号：US18106379

申请日：2023-02-06

Applicant: Applied Materials, Inc.

Inventor： Sai Abhinand ,  Michael Sorensen ,  Karthik Elumalai ,  Dimantha Rajapaksa ,  Cheng Sun ,  James S. Papanu ,  Gaurav Mehta ,  Eng Sheng Peh ,  Sri Thirunavukarasu ,  Onkara Korasiddaramaiah

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/683 ,  H01L21/82

CPC classification number: H01L21/3065 ,  H01J37/32715 ,  H01L21/6833 ,  H01L21/82 ,  H01J37/32642 ,  H01J2237/3341

Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.

公开(公告)号：US11600492B2

公开(公告)日：2023-03-07

申请号：US16709522

申请日：2019-12-10

Applicant: Applied Materials, Inc.

Inventor： Sai Abhinand ,  Michael Sorensen ,  Karthik Elumalai ,  Dimantha Rajapaksa ,  Cheng Sun ,  James S. Papanu ,  Gaurav Mehta ,  Eng Sheng Peh ,  Sri Thirunavukarasu ,  Onkara Korasiddaramaiah

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/683 ,  H01L21/82

Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.

公开(公告)号：US20210242014A1

公开(公告)日：2021-08-05

申请号：US16777610

申请日：2020-01-30

Applicant: Applied Materials, Inc.

Inventor： Wenguang Li ,  James S. Papanu

IPC: H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/78

Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.

公开(公告)号：US10903121B1

公开(公告)日：2021-01-26

申请号：US16540899

申请日：2019-08-14

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Karthik Balakrishnan ,  James S. Papanu

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L23/544 ,  H01L21/67 ,  B23K26/08 ,  B23K26/362 ,  B23K26/06

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US20180342422A1

公开(公告)日：2018-11-29

申请号：US15606456

申请日：2017-05-26

Applicant: APPLIED MATERIALS, INC.

Inventor： Wenguang Li ,  James S. Papanu ,  Wei-Sheng Lei ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar ,  Alexander N. Lerner

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/02

Abstract: Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.