公开(公告)号：US09257199B2

公开(公告)日：2016-02-09

申请号：US13949343

申请日：2013-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber

IPC: G11C29/02 ,  G11C8/08 ,  G11C11/418 ,  G11C29/12

CPC classification number: G11C29/021 ,  G11C8/08 ,  G11C11/418 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

Abstract: A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a wordline voltage that accounts for a predetermined offset of a threshold voltage of the passgate transistor. In an embodiment, the regulator circuit is a subtractor circuit that generates the wordline voltage from a reference voltage based in part on the threshold voltage variation of the passgate transistor.

Abstract translation: 本文描述了具有通道晶体管变化的金丝雀电路。 金丝雀电路包括具有多个位单元的存储器金丝雀电路。 每个位单元至少具有由字线电压驱动的通道晶体管。 金丝雀电路还包括调节器电路，其输出考虑了通路晶体管的阈值电压的预定偏移的字线电压。 在一个实施例中，调节器电路是一个减法器电路，其部分地基于通道晶体管的阈值电压变化从参考电压产生字线电压。

公开(公告)号：US20150364168A1

公开(公告)日：2015-12-17

申请号：US14307164

申请日：2014-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC: G11C7/18 ,  G11C11/406 ,  G06F12/06

CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。

公开(公告)号：US08958236B2

公开(公告)日：2015-02-17

申请号：US13749672

申请日：2013-01-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Keith A. Kasprak ,  Russell Schreiber

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/04

CPC classification number: G11C11/412 ,  G11C7/04

Abstract: An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.

Abstract translation: 装置可以包括被配置为根据电压模式操作的存储单元，与存储单元耦合的电压控制器，其中电压控制器被配置为在低电压模式和高电压模式之间改变存储单元的电压模式 以及与所述存储器单元耦合的存储器控​​制器模块，其中所述存储器控制器被配置为基于所述电压模式反转存储在所述存储器单元中的逻辑状态。

公开(公告)号：US20240005078A1

公开(公告)日：2024-01-04

申请号：US17854516

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Edward Griffith ,  Aaron Keiichi Horiuchi ,  Donald A. Clay ,  Eric William Busta ,  Hye Jung Stanford ,  Kathryn E. Wilcox ,  Ruochen Xie ,  Russell Schreiber ,  Stephen J. Dussinger ,  William Edwin Laub, JR. ,  Te-Hsuan Chen

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.

公开(公告)号：US20220415377A1

公开(公告)日：2022-12-29

申请号：US17359445

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G06F30/392

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

公开(公告)号：US11264115B2

公开(公告)日：2022-03-01

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

公开(公告)号：US11227651B2

公开(公告)日：2022-01-18

申请号：US16692714

申请日：2019-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  Russell Schreiber ,  Kyle Whittle

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/419 ,  G11C7/10 ,  G11C11/4074

Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.

公开(公告)号：US20200335142A1

公开(公告)日：2020-10-22

申请号：US16454692

申请日：2019-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak

IPC: G11C7/06 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A circuit includes a repeating series of first circuits and a repeating series of second circuits placed next to the repeating series of first circuits and interacts with corresponding portions of the first circuits in the series. The repeating series of second circuits is formed in diffusion regions and diffusion wells which extend along the direction in which the second circuits repeat. The repeating series of the first and second circuits is interrupted by at least one dummy circuit region, which occupies the space of one or more instances of the first and second repeating series. The dummy circuit region also includes taps for biasing the diffusion regions and diffusion wells of the second circuits.

公开(公告)号：US10608633B1

公开(公告)日：2020-03-31

申请号：US16553590

申请日：2019-08-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Russell Schreiber

IPC: H03K19/00 ,  H03K19/02 ,  H03K19/0175 ,  H04L25/20

Abstract: An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.

公开(公告)号：US10509752B2

公开(公告)日：2019-12-17

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G11C5/06 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065 ,  G06F13/40

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.