公开(公告)号：US07184356B2

公开(公告)日：2007-02-27

申请号：US11074801

申请日：2005-03-09

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

IPC分类号： G11C8/00

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/76 ,  G11C29/82 ,  G11C29/84 ,  G11C2029/0409 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

摘要翻译： 半导体存储器件包括：存储单元阵列，具有彼此平行布置的多个数据选择线;多个数据传输线，彼此并联设置，以与数据选择线相交;以及布置的电可重写存储器单元 在数据选择线和数据传输线之间的交叉部分; 用于驱动存储单元阵列的数据选择线的数据选择线驱动器; 连接到存储单元阵列的数据传输线的读出放大器电路，用于对数据选择线之一选择的存储器单元执行数据读取; 以及用于对存储单元阵列的数据读取进行定时控制的控制电路，用于根据存储单元阵列的所选择的数据区输出不同的至少两种类型的定时信号。

公开(公告)号：US20050204212A1

公开(公告)日：2005-09-15

申请号：US11055782

申请日：2005-02-11

申请人： Mitsuhiro Noguchi ,  Akira Goda

发明人： Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11529 ,  G06F11/1048 ,  G11C16/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/76

摘要： A data memory system includes a non-spare area having a plurality of memory cell blocks and containing pages, a spare area having a plurality of spare memory cell blocks in which data items are previously set to a certain value and containing pages, and a determination circuit which detects a data error of at least two bits when data is read out from the page of the non-spare area and determines the number of error bits in the readout page for each readout page. When the result of determination by the determination circuit indicates two or more bits, the contents of the readout page are error-corrected and programmed into the page of the spare area.

摘要翻译： 数据存储器系统包括具有多个存储单元块并且包含页面的非备用区域，具有多个备用存储单元块的备用区，其中数据项预先设置为特定值并包含页面，以及确定 电路，当从非备用区的页面读出数据时，检测至少两位的数据错误，并确定每个读出页的读出页面中的错误位的数量。 当确定电路的确定结果指示两位或多位时，读出页的内容被纠错并编程到备用区的页面中。

公开(公告)号：US20050157558A1

公开(公告)日：2005-07-21

申请号：US11007461

申请日：2004-12-09

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3445 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3468

摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.

摘要翻译： 半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果 在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中 作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。 第一参考阈值电压被设置为不同于第二参考阈值电压。

公开(公告)号：US06903422B2

公开(公告)日：2005-06-07

申请号：US10609520

申请日：2003-07-01

申请人： Akira Goda ,  Mitsuhiro Noguchi ,  Masayuki Tanaka ,  Shigehiko Saida

发明人： Akira Goda ,  Mitsuhiro Noguchi ,  Masayuki Tanaka ,  Shigehiko Saida

IPC分类号： H01L27/10 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： A semiconductor integrated circuit is disclosed, which includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and having a first gate insulating layer of a stacked structure which includes a silicon nitride layer to become a charge storage layer, and a transistor formed on the semiconductor substrate and having a second gate insulating layer. Here, source and drain diffused layers of the memory cell are covered with a part of the first gate insulating layer, and metal silicide layers are formed on surfaces of source and drain diffused layers of the transistor.

摘要翻译： 公开了一种半导体集成电路，其包括半导体衬底，形成在半导体衬底上的存储单元，并且具有堆叠结构的第一栅极绝缘层，其包括形成电荷存储层的氮化硅层，以及形成在 半导体衬底并具有第二栅极绝缘层。 这里，存储单元的源极和漏极扩散层被第一栅极绝缘层的一部分覆盖，并且金属硅化物层形成在晶体管的源极和漏极扩散层的表面上。

公开(公告)号：US06870773B2

公开(公告)日：2005-03-22

申请号：US10796180

申请日：2004-03-10

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3445 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3468

摘要： A semiconductor memory device includes a first memory cell block capable of rewriting data and having at least one first memory cell, and a second memory cell block capable of rewriting data and having at least one second memory cell adjoining the first memory cell. A data writing method for the semiconductor memory device includes writing data into the first memory cell, writing data into the second memory cell following writing the data into the first memory cell, verifying the data of the first memory cell after writing the data into the second memory cell, and rewriting the data into the first memory cell when insufficiency of the data of the first memory cell as a result of verifying the data of the first memory cell.

摘要翻译： 半导体存储器件包括能够重写数据并具有至少一个第一存储单元的第一存储单元块和能够重写数据并具有与第一存储单元相邻的至少一个第二存储单元的第二存储单元块。 一种用于半导体存储器件的数据写入方法，包括将数据写入第一存储单元，将数据写入第一存储单元之后将数据写入第二存储单元，在将数据写入第二存储单元之后，验证第一存储单元的数据 并且当由于验证第一存储单元的数据而使第一存储器单元的数据不足时将数据重新写入第一存储器单元。

公开(公告)号：US20050051831A1

公开(公告)日：2005-03-10

申请号：US10890132

申请日：2004-07-14

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

公开(公告)号：US20050006696A1

公开(公告)日：2005-01-13

申请号：US10850408

申请日：2004-05-21

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Masayuki Tanaka

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Masayuki Tanaka

IPC分类号： G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/148 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： A semiconductor memory having an electrically writable/erasable memory cell includes a first gate insulating layer made from a compound containing silicon and oxygen; a first charge-storage layer being in contact with the first gate insulating layer made from a silicon nitride film, a silicon oxynitride film, or an alumina film; a second insulating layer thicker than the first gate insulting layer; a second charge-storage layer being in contact with the second insulating layer; a third insulating layer thicker than the first gate insulating layer being in contact with the second charge-storage layer; and a control electrode upon the third insulating layer.

摘要翻译： 具有电可写/可擦除存储单元的半导体存储器包括由含硅和氧的化合物制成的第一栅极绝缘层; 与由氮化硅膜，氮氧化硅膜或氧化铝膜构成的第一栅极绝缘层接触的第一电荷存储层; 比第一栅极绝缘层厚的第二绝缘层; 与第二绝缘层接触的第二电荷存储层; 比所述第一栅极绝缘层更厚的与所述第二电荷存储层接触的第三绝缘层; 以及在所述第三绝缘层上的控制电极。

公开(公告)号：US20090267136A1

公开(公告)日：2009-10-29

申请号：US12498149

申请日：2009-07-06

申请人： Akira Goda ,  Mitsuhiro Noguchi

发明人： Akira Goda ,  Mitsuhiro Noguchi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.

摘要翻译： 提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量， 并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。 在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。 在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件 用于高压晶体管的隔离槽23宽而深。 以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

公开(公告)号：US20080122098A1

公开(公告)日：2008-05-29

申请号：US12000396

申请日：2007-12-12

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

公开(公告)号：US07245534B2

公开(公告)日：2007-07-17

申请号：US11135415

申请日：2005-05-24

申请人： Akira Goda ,  Mitsuhiro Noguchi ,  Minori Kajimoto ,  Yuji Takeuchi

发明人： Akira Goda ,  Mitsuhiro Noguchi ,  Minori Kajimoto ,  Yuji Takeuchi

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和 栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。 字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离 字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。