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    Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact
    21.
    发明申请
    Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact 有权
    屏蔽栅极沟槽（SGT）MOSFET电池采用肖特基源极接触

    公开(公告)号：US20090072301A1

    公开(公告)日：2009-03-19

    申请号：US12313305

    申请日：2008-11-18

    申请人： Anup Bhalla ,  Sik K. Lui

    发明人： Anup Bhalla ,  Sik K. Lui

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

    摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

    摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 至少一个有源电池还包括在沟槽之间开放的沟槽的源极触点，其中沟槽的源极触点通过源极区域开放到主体区域中，用于将源区域电连接到设置在绝缘层顶部的源极金属，其中沟槽底部 沟槽源极接触表面进一步用导电材料覆盖，以用作所述活性电池中的集成肖特基势垒二极管。 屏蔽结构设置在底部并与沟槽栅绝缘，以为沟槽栅极和肖特基二极管提供屏蔽效应。

    MOSFET for synchronous rectification
    22.
    发明授权
    MOSFET for synchronous rectification 有权
    MOSFET用于同步整流

    公开(公告)号：US07221195B2

    公开(公告)日：2007-05-22

    申请号：US11083470

    申请日：2005-03-18

    申请人： Anup Bhalla ,  Sik K. Lui

    发明人： Anup Bhalla ,  Sik K. Lui

    IPC分类号： H03B1/00

    CPC分类号： H01L27/088 ,  H01L27/0629 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2223/6644 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48247 ,  H03K17/165 ,  H01L2924/00

    摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

    摘要翻译： 本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。 并联FET分流瞬态电流。 分流FET用于防止MOSFET器件无意中导通。 当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。 通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。

    Mosfet using gate work function engineering for switching applications
    25.
    发明申请
    Mosfet using gate work function engineering for switching applications 有权
    Mosfet使用门功能工程开关应用

    公开(公告)号：US20110097885A1

    公开(公告)日：2011-04-28

    申请号：US12928987

    申请日：2010-12-23

    申请人： Anup Bhalla ,  Sik K. Lui

    发明人： Anup Bhalla ,  Sik K. Lui

    IPC分类号： H01L21/28

    CPC分类号： H01L29/7813 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7811

    摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.

    摘要翻译： 本发明公开了一种新的MOSFET器件。 通过在N-MOSFET器件中实现P掺杂栅极，MOSFET器件具有通过制造具有较高栅极功能功能的MOSFET获得的改进的操作特性。 P型栅极增加阈值电压并移位C-Vds特性。 因此，减少的Cgd实现了抑制拍摄的目的，并解决了上述困难。 与常规技术不同，实现了电容Cgd的减小，而不需要复杂的制造工艺和凹陷电极的控制。

    MOSFET using gate work function engineering for switching applications
    26.
    发明授权
    MOSFET using gate work function engineering for switching applications 有权
    MOSFET采用门极功能工程用于开关应用

    公开(公告)号：US07863675B2

    公开(公告)日：2011-01-04

    申请号：US11999167

    申请日：2008-03-22

    申请人： Anup Bhalla ,  Sik K. Lui

    发明人： Anup Bhalla ,  Sik K. Lui

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7811

    摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.

    摘要翻译： 本发明公开了一种新的MOSFET器件。 通过在N-MOSFET器件中实现P掺杂栅极，MOSFET器件具有通过制造具有较高栅极功能功能的MOSFET获得的改进的操作特性。 P型栅极增加阈值电压并移位C-Vds特性。 因此，减少的Cgd实现了抑制拍摄的目的，并解决了上述困难。 与常规技术不同，实现了电容Cgd的减小，而不需要复杂的制造工艺和凹陷电极的控制。

    MOSFET using gate work function engineering for switching applications
    28.
    发明申请
    MOSFET using gate work function engineering for switching applications 有权
    MOSFET采用门极功能工程用于开关应用

    公开(公告)号：US20080173956A1

    公开(公告)日：2008-07-24

    申请号：US11999167

    申请日：2008-03-22

    申请人： Anup Bhalla ,  Sik K. Lui

    发明人： Anup Bhalla ,  Sik K. Lui

    IPC分类号： H01L29/78 ,  H01L21/3205

    CPC分类号： H01L29/7813 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7811

    摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.

    摘要翻译： 本发明公开了一种新的MOSFET器件。 通过在N-MOSFET器件中实现P掺杂栅极，MOSFET器件具有通过制造具有较高栅极功能功能的MOSFET获得的改进的操作特性。 P型栅极增加阈值电压并移位C-Vds特性。 因此，减少的Cgd实现了抑制拍摄的目的，并解决了上述困难。 与传统技术不同，实现了电容Cgd的减小，而不需要复杂的制造工艺和凹陷电极的控制。

    Low cost power MOSFET with current monitoring
    29.
    发明授权
    Low cost power MOSFET with current monitoring 有权
    低成本功率MOSFET，具有电流监控功能

    公开(公告)号：US07122882B2

    公开(公告)日：2006-10-17

    申请号：US10979410

    申请日：2004-11-02

    申请人： Sik K. Lui ,  Anup Bhalla

    发明人： Sik K. Lui ,  Anup Bhalla

    IPC分类号： H01L23/495

    CPC分类号： H01L24/91 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/16 ,  H01L29/7834 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A semiconductor integrated circuit package having a common source current sensing circuit includes a main die having an integrated circuit, the main die including a source bonding pad and a gate bonding pad disposed on an upper surface, a leadframe having a leadframe pad disposed under the main die, and a monitoring die including a source bonding pad and a gate bonding pad disposed on an upper surface, the monitoring die being coupled to the main die in such manner that the main die source bonding pad is coupled to the monitoring die source bonding pad and the main die gate bonding pad is coupled to the monitoring die gate bonding pad and such that the main die and monitoring die upper surfaces are adjacent to one another.

    摘要翻译： 具有公共源极电流检测电路的半导体集成电路封装包括具有集成电路的主管芯，所述主管芯包括源极接合焊盘和设置在上表面上的栅极接合焊盘，引线框架，其具有设置在主体下方的引线框架焊盘 管芯，以及包括设置在上表面上的源极焊盘和栅极焊盘的监测管芯，所述监测管芯以这样的方式联接到所述主管芯，使得所述主管芯源焊盘与所述监测管芯焊接焊盘 并且主晶片栅极焊盘耦合到监测裸片栅极焊盘，使得主裸片和监测裸片上表面彼此相邻。

    Shielded gate trench (SGT) MOSFET devices and manufacturing processes
    30.
    发明授权
    Shielded gate trench (SGT) MOSFET devices and manufacturing processes 有权

    公开(公告)号：US08431989B2

    公开(公告)日：2013-04-30

    申请号：US13066947

    申请日：2011-04-28

    申请人： Anup Bhalla ,  Sik K. Lui

    发明人： Anup Bhalla ,  Sik K. Lui

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811

    摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.