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    Memory System with Shared File System
    21.
    发明申请
    Memory System with Shared File System 有权
    具有共享文件系统的内存系统

    公开(公告)号：US20150106410A1

    公开(公告)日：2015-04-16

    申请号：US14050737

    申请日：2013-10-10

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Sasha Paley ,  Avraham Poza Meir

    IPC: G06F3/06 ,  G06F12/08 ,  G06F17/30

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0671 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0833 ,  G06F17/30218 ,  G06F2212/621

    Abstract: An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.

    Abstract translation: 一种装置包括非易失性存储器和处理器。 处理器被配置为从主机接收用于在非易失性存储器中存储数据的命令，以进一步从主机接收用于存储在非易失性存储器中的文件系统（FS）信息，所述文件系统（FS）信息指定 在主机的FS中的数据，从主机接收授权处理器许可和访问和修改FS信息的能力的指令，以及使用该指令访问FS信息，以便管理数据的存储 在非易失性内存中。

    UNEVEN WEAR LEVELING IN ANALOG MEMORY DEVICES
    22.
    发明申请
    UNEVEN WEAR LEVELING IN ANALOG MEMORY DEVICES 有权
    在模拟记忆体设备中耐磨损

    公开(公告)号：US20150012686A1

    公开(公告)日：2015-01-08

    申请号：US13935746

    申请日：2013-07-05

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Shai Ojalvo ,  Yoav Kasorla ,  Naftali Sommer

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7211

    Abstract: A method for data storage in a memory that includes multiple analog memory cells, includes defining, based on a characteristic of the memory cells, an uneven wear leveling scheme that programs and erases at least first and second subsets of the memory cells with respective different first and second Programming and Erasure (P/E) rates. Data is stored in the memory in accordance with the uneven wear leveling scheme.

    Abstract translation: 一种用于在包括多个模拟存储器单元的存储器中的数据存储的方法，包括基于所述存储器单元的特性定义不均匀磨损平衡方案，所述不均匀磨损均衡方案以相应不同的第一方式来编程和擦除所述存储器单元的至少第一和第二子集 和第二个编程和擦除（P / E）率。 根据不均匀的磨损均衡方案将数据存储在存储器中。

    Independent Management of Data and Parity Logical Block Addresses
    23.
    发明申请
    Independent Management of Data and Parity Logical Block Addresses 审中-公开
    数据和奇偶校验逻辑块地址的独立管理

    公开(公告)号：US20140365821A1

    公开(公告)日：2014-12-11

    申请号：US14468527

    申请日：2014-08-26

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Oren Golov ,  Naftali Sommer ,  Moshe Neerman

    IPC: G06F11/10

    CPC classification number: G06F11/108 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1068 ,  G06F11/1096 ,  G06F12/0246 ,  G06F12/06 ,  G06F2211/1059 ,  G06F2212/7205

    Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

    Abstract translation: 数据存储方法包括在与存储在存储器中的各个逻辑地址相关联的一组数据项中识别与包含应用数据的数据项相关联的逻辑地址的第一子集，以及与包含应用数据的逻辑地址相关联的第二子集 包含已经通过应用数据计算的奇偶校验信息的数据项。 与第一识别的子集相关联的数据项存储在存储器的一个或多个第一物理存储器区域中，并且与第二识别的子集相关联的数据项存储在存储器的一个或多个第二物理存储器区域中，不同于 第一个物理内存区域。 在第一物理存储器区域和第二物理存储器区域中独立地执行存储器管理任务。

    ENHANCED DATA STORAGE IN 3-D MEMORY USING STRING-SPECIFIC SOURCE-SIDE BIASING
    24.
    发明申请
    ENHANCED DATA STORAGE IN 3-D MEMORY USING STRING-SPECIFIC SOURCE-SIDE BIASING 有权
    3-D存储器中的数据存储增强使用特定的源极偏置

    公开(公告)号：US20140313832A1

    公开(公告)日：2014-10-23

    申请号：US13865351

    申请日：2013-04-18

    Applicant: APPLE INC.

    Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

    Abstract translation: 一种方法包括将数据存储在存储器中，其包括以具有与位线相关联的第一维度的三维（3-D）配置布置的多个模拟存储器单元串，与字线相关联的第二维度和与第三维度相关联的第三维度 具有部分，使得每个字符串与相应的位线和相应的部分相关联，并且包括连接到各个字线的多个存储器单元。 对于一组字符串，对组中字符串的属性的各个值进行评估。 根据属性的各个值，针对组中的各个串来计算源侧电压，并且组中的串的各个源侧被相应的源极侧电压偏置。 当串被相应的源侧电压偏置时，对组中的串执行存储器操作。

    Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block
    29.
    发明授权
    Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block 有权
    识别存储器块中的字线到基板和字线到字线的短路事件

    公开(公告)号：US09330783B1

    公开(公告)日：2016-05-03

    申请号：US14572818

    申请日：2014-12-17

    Applicant: APPLE INC.

    Inventor： Barak Rotbard ,  Avraham Poza Meir ,  Eyal Gurgi ,  Yael Shur ,  Barak Baum

    IPC: G11C29/00 ,  G11C29/02 ,  G11C16/26 ,  G11C16/14

    CPC classification number: G11C29/025 ,  G11C29/006 ,  G11C2029/1202

    Abstract: An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.

    Abstract translation: 一种装置包括存储器和存储器控制器。 该存储器包括一个包含通过字线连接的存储器单元的存储块。 存储器控制器被配置为将数据存储在存储器单元中，并且通过识别存储器块中的至少给定字线的性能特性相对于性能特性的偏差来识别存储器块中的可疑短路事件 剩余字线在存储器块中。

    Mitigating reliability degradation of analog memory cells during long static and erased state retention
    30.
    发明授权
    Mitigating reliability degradation of analog memory cells during long static and erased state retention 有权
    在长静态和擦除状态保持期间，减轻模拟存储单元的可靠性降级

    公开(公告)号：US09236132B2

    公开(公告)日：2016-01-12

    申请号：US14249448

    申请日：2014-04-10

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

    IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

    Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

    Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。

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