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公开(公告)号:US11189479B2
公开(公告)日:2021-11-30
申请号:US16865514
申请日:2020-05-04
Applicant: Applied Materials, Inc.
Inventor: Benjamin Colombeau , Johanes F. Swenberg , Steven C. H. Hung
IPC: H01L21/469 , H01L23/58 , H01L21/02 , H01L21/762 , H01L21/768
Abstract: A method of forming an electronic device is disclosed. The method comprises forming a barrier layer on a silicon layer, and depositing a silicon oxide layer on the barrier layer. The formation of the barrier layer on the silicon layer minimizes parasitic oxidation of the underlying silicon layer and minimizes defects in the silicon layer.
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公开(公告)号:US10347492B2
公开(公告)日:2019-07-09
申请号:US15874132
申请日:2018-01-18
Applicant: Applied Materials, Inc.
Inventor: Steven C. H. Hung , Johanes S. Swenberg , Wei Liu , Houda Graoui
IPC: H01L21/28 , H01L21/321 , H01L29/49 , H01L21/285 , H01L21/67 , H01L29/51
Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.
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公开(公告)号:US12288717B2
公开(公告)日:2025-04-29
申请号:US18581598
申请日:2024-02-20
Applicant: Applied Materials, Inc.
Inventor: Srinivas Gandikota , Steven C. H. Hung , Srinivas D. Nemani , Yixiong Yang , Susmit Singha Roy , Nikolaos Bekiaris
IPC: H01L21/768 , H01L23/48
Abstract: A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.
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公开(公告)号:US12183798B2
公开(公告)日:2024-12-31
申请号:US17528863
申请日:2021-11-17
Applicant: Applied Materials, Inc.
Inventor: Steven C. H. Hung , Benjamin Colombeau , Myungsun Kim , Srinivas Gandikota , Yixiong Yang , Jacqueline Samantha Wrench , Yong Yang
IPC: H01L29/423 , H01L29/06 , H01L29/78 , H01L29/786
Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.
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公开(公告)号:US12112951B2
公开(公告)日:2024-10-08
申请号:US17673905
申请日:2022-02-17
Applicant: Applied Materials, Inc.
Inventor: Srinivas Gandikota , Yixiong Yang , Steven C. H. Hung , Tianyi Huang , Seshadri Ganguli
IPC: H01L21/28 , H01L21/324 , H01L21/8238
CPC classification number: H01L21/28088 , H01L21/28185 , H01L21/324 , H01L21/823807 , H01L21/823857
Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.
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公开(公告)号:US12020982B2
公开(公告)日:2024-06-25
申请号:US17587525
申请日:2022-01-28
Applicant: Applied Materials, Inc.
Inventor: Srinivas Gandikota , Steven C. H. Hung , Srinivas D. Nemani , Yixiong Yang , Susmit Singha Roy , Nikolaos Bekiaris
IPC: H01L21/768 , H01L23/48
CPC classification number: H01L21/76864 , H01L21/76898 , H01L23/481
Abstract: A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.
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公开(公告)号:US11955332B2
公开(公告)日:2024-04-09
申请号:US17843541
申请日:2022-06-17
Applicant: Applied Materials, Inc.
Inventor: Srinivas Gandikota , Yixiong Yang , Jacqueline Samantha Wrench , Yong Yang , Steven C. H. Hung
CPC classification number: H01L21/02247 , H01L21/02043 , H01L21/02274 , H01L21/28185 , H01L21/28202 , H01L21/67023 , H01L21/67207
Abstract: A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.
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公开(公告)号:US11450759B2
公开(公告)日:2022-09-20
申请号:US17037941
申请日:2020-09-30
Applicant: Applied Materials, Inc.
Inventor: Steven C. H. Hung , Benjamin Colombeau , Andy Lo , Byeong Chan Lee , Johanes F. Swenberg , Theresa Kramer Guarini , Malcolm J. Bevan
IPC: H01L29/66 , H01L21/02 , H01L29/423 , C30B29/06 , C30B29/52 , C23C8/02 , C23C8/16 , C23C8/80 , C23C16/56 , C23C16/455
Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.
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公开(公告)号:US20220077298A1
公开(公告)日:2022-03-10
申请号:US17013161
申请日:2020-09-04
Applicant: Applied Materials, Inc.
Inventor: SRINIVAS GANDIKOTA , Steven C. H. Hung , Mandyam Sriram , Jacqueline S. Wrench , Yixiong Yang , Yong Yang
Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.
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公开(公告)号:US11245022B2
公开(公告)日:2022-02-08
申请号:US16876276
申请日:2020-05-18
Applicant: Applied Materials, Inc.
Inventor: Yongjing Lin , Karla M. Bernal Ramos , Luping Li , Shih Chung Chen , Jacqueline S. Wrench , Yixiong Yang , Steven C. H. Hung , Srinivas Gandikota , Naomi Yoshida , Lin Dong
Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).
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