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公开(公告)号：US09484364B2
公开(公告)日：2016-11-01
申请号：US14386209
申请日：2013-12-03
发明人： Jing Li , Wenyu Zhang , Jiaxiang Zhang
IPC分类号： H01L27/12 , H01L29/417 , H01L23/50
CPC分类号： H01L27/124 , G02F1/136286 , G02F2201/40 , H01L23/50 , H01L27/1222 , H01L27/1288 , H01L29/41733 , H01L29/41741 , H01L29/41775 , H01L29/78642
摘要： An array substrate and a display device are presented. The array substrate includes: a base substrate and a plurality of thin film transistor units located on the base substrate, wherein, the thin film transistor unit includes: a first gate electrode located on the base substrate, a gate insulating layer located on the first gate electrode, a drain electrode disposed in the same layer as the first gate electrode, an active layer located on the drain electrode, a source electrode located on the active layer, a first transparent conductive layer is provided between the base substrate and the first gate electrode and the drain electrode that are disposed in the same layer, and the gate insulating layer is also disposed between the first gate electrode plus the first transparent conductive layer beneath it and the drain electrode plus the first transparent conductive layer beneath it.
摘要翻译： 呈现阵列基板和显示装置。 阵列基板包括：基底基板和位于基底基板上的多个薄膜晶体管单元，其中，薄膜晶体管单元包括：位于基底基板上的第一栅电极，位于第一栅极上的栅极绝缘层 电极，设置在与第一栅电极相同的层中的漏电极，位于漏电极上的有源层，位于有源层上的源电极，第一透明导电层设置在基底基板和第一栅电极之间 和漏电极，并且栅绝缘层也设置在第一栅电极与其下的第一透明导电层之间，漏电极加上其下的第一透明导电层。
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22.发明申请CAPACITIVE TOUCH PANEL, DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE TOUCH PANEL 有权电容触控面板，显示装置及制造触控面板的方法公开(公告)号：US20150145811A1
公开(公告)日：2015-05-28
申请号：US14345040
申请日：2013-07-10
发明人： Jiaxiang Zhang , Xiaohui Jiang , Jian Guo , Xu Chen
CPC分类号： G06F3/044 , C23F1/02 , G06F2203/04103 , G06F2203/04112 , H05K3/06
摘要： An embodiment of the present application discloses a capacitive touch panel including a base substrate, on which a plurality of transparent conductive patters being capable of transmitting touch signals and not overlapping with each are provided, and each transparent conductive pattern is an integrated pattern made of a same material layer. An embodiment of the present application further provides a method for manufacturing a capacitive touch panel, which includes forming a plurality of transparent conductive patterns on a base substrate through one mask patterning process. An embodiment of the present application further includes a display device comprising the capacitive touch panel as described above. An embodiment of the present application can save masks and can manufacture capacitive touch panels at a low cost. Furthermore, the embodiments of the present application have advantages of high production efficiency and of high yield rate.
摘要翻译： 本申请的一个实施方案公开了一种电容式触摸屏，其包括基底，多个透明导电图案能够传输触摸信号并且不与每个透明导电图案重叠，并且每个透明导电图案是由 相同的材料层。 本申请的实施例还提供了一种用于制造电容式触摸屏的方法，其包括通过一个掩模图案化工艺在基底衬底上形成多个透明导电图案。 本申请的实施例还包括包括如上所述的电容式触摸面板的显示装置。 本申请的实施例可以节省掩模并且可以以低成本制造电容式触摸面板。 此外，本申请的实施方案具有生产效率高，产率高的优点。
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公开(公告)号：US09761615B2
公开(公告)日：2017-09-12
申请号：US14769658
申请日：2014-10-27
发明人： Xiaohui Jiang , Changjiang Yan , Jiaxiang Zhang
IPC分类号： H01L27/12 , H01L21/77 , H01L21/311 , H01L21/768
CPC分类号： H01L27/1248 , H01L21/31116 , H01L21/31138 , H01L21/76816 , H01L21/77 , H01L27/12 , H01L27/1244 , H01L27/1262 , Y02P80/30
摘要： An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises: a base substrate (1), thin-film transistors (TFTs), an isolation layer (10) and an organic resin layer (8) formed on the base substrate (1), and a common electrode layer (12) formed on the organic resin layer (8). The isolation layer (10) covers source electrodes (6) and drain electrodes (7) of the TFTs; the organic resin layer (8) covers the isolation layer (10) and is provided with first through holes (9) corresponding to the drain electrodes (7) of the TFTs; the isolation layer (10) is provided with second through holes (11) communicated with the first through holes (9) to expose partial drain electrodes (7); and the dimension of the second through holes (11) is greater than that of the first through holes (9). The array substrate, the manufacturing method thereof and the display device resolve the problem of forming dark dots, ensure the product quality, reduce the waste of production materials, and reduce the production cost.
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公开(公告)号：US09740053B2
公开(公告)日：2017-08-22
申请号：US14386592
申请日：2013-11-14
发明人： Jiaxiang Zhang
IPC分类号： G02F1/1335 , G02F1/1339 , G02F1/1368 , H01L27/12 , H01L29/786
CPC分类号： G02F1/13394 , G02F1/1368 , H01L27/1225 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L29/66969 , H01L29/7869
摘要： Embodiments of the disclosure provide an array substrate and a fabrication method thereof, and a display device. The array substrate includes: a base substrate and a switch unit disposed on the base substrate. The array substrate further includes: a passivation layer disposed on the base substrate and a spacer disposed on the passivation layer; and the spacer corresponds to the switch unit.
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公开(公告)号：US09437149B2
公开(公告)日：2016-09-06
申请号：US14366132
申请日：2013-12-12
发明人： Jiaxiang Zhang
IPC分类号： G09G3/36 , G02F1/1362
CPC分类号： G09G3/3648 , G02F1/1362 , G09G2300/0426 , G09G2300/0809 , G09G2320/0223 , G09G2320/028
摘要： An array substrate and a display are provided, and the array substrate includes: a substrate; a pixel region, provided on the substrate; a plurality of data lines, formed on the substrate; a plurality of gate signal lines, formed on the substrate and configured to apply a gate signal; a plurality of pixel units, located in the pixel region and defined by crossing of the plurality of data lines and the plurality of gate signal lines; and at least one leading wire, provided at the periphery of the pixel region and configured to transmit the gate signal, wherein two ends of each of the plurality of gate signal lines near the periphery of the pixel region are connected with one leading wire through a first thin film transistor and a second thin film transistor respectively.
摘要翻译： 提供了阵列基板和显示器，阵列基板包括：基板; 设置在基板上的像素区域; 多个数据线，形成在所述基板上; 多个栅极信号线，形成在所述基板上并被配置为施加栅极信号; 多个像素单元，位于所述像素区域中，并且由所述多条数据线和所述多条栅极信号线的交叉限定; 以及至少一个引线，设置在所述像素区域的周边并且被配置为发送所述栅极信号，其中，所述多个栅极信号线中的每一个靠近所述像素区域的周边的两端通过一个引线连接通过 第一薄膜晶体管和第二薄膜晶体管。
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公开(公告)号：US20240332460A1
公开(公告)日：2024-10-03
申请号：US18246452
申请日：2022-06-30
发明人： Jiaxiang Zhang , Ke Wang , Zhanfeng Cao
IPC分类号： H01L33/44 , H01L25/075 , H01L33/38 , H01L33/62
CPC分类号： H01L33/44 , H01L25/0753 , H01L33/382 , H01L33/62 , H01L2933/0025
摘要： A display substrate, a method for manufacturing the display substrate, and a display device are provided. The display substrate includes: a base substrate; a metal layer on the base substrate, including a copper layer having a first thickness; an anti-oxidation layer on a side of the metal layer away from the base substrate, having a second thickness; and a light emitting diode on a side of the anti-oxidation layer away from the base substrate, including at least one electrode electrically connected to the metal layer, where the first thickness of the metal layer is larger than the second thickness of the anti-oxidation layer.
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27.发明授权公开(公告)号：US10128272B2
公开(公告)日：2018-11-13
申请号：US14421279
申请日：2014-04-28
发明人： Jiaxiang Zhang , Jian Guo , Xiaohui Jiang , Changjiang Yan
IPC分类号： H01L27/12 , H01L21/84 , G02F1/1335 , G02F1/1343
摘要： Disclosed are a TFT array substrate, a method for fabricating the same and a display device. The TFT array substrate includes a plurality of pixel units, each of the plurality of pixel units includes a common electrode (9). The common electrode (9), is comb-shaped, and includes a plurality of strip electrodes and a plurality of slits. Each of the strip electrodes is configured for reflecting light incident on the strip electrode, and each of the slits is configured for transmitting light incident on the slit. As the comb-shaped common electrode with both a reflective region and a transmissive region is formed through a single patterning process, the fabrication process is simplified and the fabrication cost and difficulty are reduced.
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28.发明授权公开(公告)号：US09583508B2
公开(公告)日：2017-02-28
申请号：US14499502
申请日：2014-09-29
发明人： Xiaohui Jiang , Jian Guo , Jiaxiang Zhang , Zongmin Tian
IPC分类号： H01L27/12 , H01L29/66 , H01L29/423 , H01L29/786 , H01L29/417 , H01L21/3213 , H01L21/308 , H01L21/027 , H01L21/311
CPC分类号： H01L27/1222 , H01L21/0273 , H01L21/308 , H01L21/31138 , H01L21/32133 , H01L21/32136 , H01L21/32139 , H01L27/1259 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/66765 , H01L29/78669 , H01L29/78678
摘要： The present invention discloses an array substrate, a preparation method for the array substrate, and a display device, wherein the array substrate comprises a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, and a pixel electrode arranged on a substrate, the active layer includes an electric conduction area, a coverage area covered by the source electrode and the drain electrode, and an exposure area surrounding the coverage area, and the pixel electrode is lapped on the upper surfaces of the drain electrode, the exposure area of the active layer, and the gate insulation layer. According to the present invention, the pixel electrode breaks in the area, with the large gradient angle, of the drain electrode caused by slip-down due to gravity can be avoided, and the lap joint for the pixel electrode and the drain electrode is effectively facilitated.
摘要翻译： 本发明公开了阵列基板，阵列基板的制造方法以及显示装置，其中阵列基板包括栅电极，栅绝缘层，有源层，源电极和漏极，以及像素 电极布置在基板上，有源层包括导电区域，由源电极和漏电极覆盖的覆盖区域以及覆盖区域周围的曝光区域，并且像素电极在漏极的上表面上重叠 电极，有源层的曝光面积和栅极绝缘层。 根据本发明，可以避免由于重力而引起的由下降引起的漏电极的大的梯度角的区域中的像素电极断裂，并且用于像素电极和漏极的搭接接头有效地 方便了
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29.发明授权Thin film transistor, array substrate and method of fabricating the same, and display device 有权薄膜晶体管，阵列基板及其制造方法以及显示装置公开(公告)号：US09570629B2
公开(公告)日：2017-02-14
申请号：US14400128
申请日：2013-12-04
发明人： Jiaxiang Zhang , Jian Guo , Xiaohui Jiang
IPC分类号： H01L29/10 , H01L29/786 , H01L29/417 , H01L29/423 , H01L27/12 , H01L29/24
CPC分类号： H01L29/78696 , H01L27/1225 , H01L27/124 , H01L27/127 , H01L29/24 , H01L29/41733 , H01L29/42384 , H01L29/66969 , H01L29/78606 , H01L29/78618 , H01L29/7869
摘要： The embodiments of the present invention provide a thin film transistor including a gate, an upper active layer, a lower active layer, an upper source, a lower source, an upper drain and a lower drain. The upper active layer and the lower active layer are disposed at an upper side and a lower side of the gate, respectively, the lower source and the lower drain are connected to the lower active layer, respectively, and the upper source and the upper drain are connected to the upper active layer, respectively. The embodiments of the present invention also provide an array substrate including the thin film transistor, a method of fabricating the array substrate, and a display device including the array substrate.
摘要翻译： 本发明的实施例提供一种薄膜晶体管，其包括栅极，上有源层，下有源层，上源极，下源极，上漏极和下漏极。 上有源层和下有源层分别设置在栅极的上侧和下侧，下源极和下漏极分别连接到下有源层，并且上源极和上漏极 分别连接到上活性层。 本发明的实施例还提供了包括薄膜晶体管的阵列基板，制造阵列基板的方法以及包括阵列基板的显示装置。
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30.发明授权Array substrate, display device and manufacturing method of the array substrate 有权阵列基板，显示装置及阵列基板的制造方法公开(公告)号：US09543324B2
公开(公告)日：2017-01-10
申请号：US14386651
申请日：2013-12-03
发明人： Changjiang Yan , Jiaxiang Zhang , Jian Guo , Zhenyu Xie , Xu Chen
IPC分类号： H01L29/10 , H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1288 , H01L29/66765 , H01L29/78669
摘要： An array substrate, a display device and a manufacturing method of the array substrate. The array substrate includes: a base substrate (1) and a plurality of pixel units located on the base substrate (1), each of the pixel units including a thin film transistor unit. The thin film transistor unit includes: a gate electrode located on the base substrate (1), a gate insulating layer (3) located on the gate electrode, an active layer (4) located on the gate insulating layer (3) and opposed to the gate electrode in position, an ohmic layer (5) located on the active layer (4), a source electrode (6a) and a drain electrode (6b) that are located on the ohmic layer (5) and a resin passivation layer (8) that are located on the source electrode (6a) and the drain electrode (6b) and covers the substrate.
摘要翻译： 阵列基板，显示装置以及阵列基板的制造方法。 阵列基板包括：基底基板（1）和位于基底基板（1）上的多个像素单元，每个像素单元包括薄膜晶体管单元。 所述薄膜晶体管单元包括：位于所述基底基板（1）上的栅极电极，位于所述栅电极上的栅极绝缘层（3），位于所述栅极绝缘层（3）上的有源层（4） 位于位置的栅电极，位于有源层（4）上的欧姆层（5），位于欧姆层（5）上的源极（6a）和漏电极（6b）和树脂钝化层 8），其位于源电极（6a）和漏电极（6b）上并覆盖基板。
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