公开(公告)号：US20130277752A1

公开(公告)日：2013-10-24

申请号：US13976075

申请日：2011-12-20

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/28185 ,  H01L21/28525 ,  H01L21/28575 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

公开(公告)号：US20120161321A1

公开(公告)日：2012-06-28

申请号：US12978359

申请日：2010-12-23

申请人： Michael G. Haverty ,  Sadasivan Shankar ,  Tahir Ghani ,  Seongjun Park

发明人： Michael G. Haverty ,  Sadasivan Shankar ,  Tahir Ghani ,  Seongjun Park

IPC分类号： H01L23/482 ,  H01L21/3205 ,  H01L21/283 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/41791 ,  H01L21/283 ,  H01L21/3205 ,  H01L23/482 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.

摘要翻译： 公开了用于在硅半导体器件中形成接触的技术。 在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。 在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。 在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。 这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。

公开(公告)号：US20110156107A1

公开(公告)日：2011-06-30

申请号：US12655408

申请日：2009-12-30

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US20110147848A1

公开(公告)日：2011-06-23

申请号：US12655085

申请日：2009-12-23

申请人： Kelin J. Kuhn ,  Tahir Ghani ,  Justin S. Sandford

发明人： Kelin J. Kuhn ,  Tahir Ghani ,  Justin S. Sandford

IPC分类号： H01L27/088 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/823431 ,  H01L27/0886

摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming transistor fins of differing heights to obtain a performance improvement for a given type of integrated circuit within the microelectronic device.

摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施例中，本主题涉及形成不同高度的晶体管鳍片，以获得微电子器件内的给定类型的集成电路的性能改进。

公开(公告)号：US20110147842A1

公开(公告)日：2011-06-23

申请号：US12646518

申请日：2009-12-23

申请人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

发明人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

摘要翻译： 具有低寄生电阻的通道应变多栅极晶体管及其制造方法。 可以在具有栅极耦合侧壁高度（Hsi）的半导体鳍片上形成栅极堆叠，蚀刻速率控制掺杂剂可以注入到与栅极堆叠相邻的半导体鳍片的源极/漏极区域中并且被注入到源极/漏极 半导体鳍片的延伸区域。 可以蚀刻掺杂散热片区域以除去等于沟道区域附近的至少Hsi的半导体鳍片的厚度并形成源极/漏极延伸底切。 可以在暴露的半导体衬底上生长材料以形成填充源极/漏极延伸底切区域的再生长源极/漏极鳍区域。

公开(公告)号：US20110147828A1

公开(公告)日：2011-06-23

申请号：US12643912

申请日：2009-12-21

申请人： Anand S. Murthy ,  Daniel Bourne Aubertine ,  Tahir Ghani ,  Abhijit Javant Pethe

发明人： Anand S. Murthy ,  Daniel Bourne Aubertine ,  Tahir Ghani ,  Abhijit Javant Pethe

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28079 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

摘要： Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

摘要翻译： 本发明的实施例描述了半导体器件上的外延区域。 在一个实施例中，通过循环沉积蚀刻工艺将外延区域沉积到衬底上。 在循环沉积 - 蚀刻工艺期间在间隔物下方产生的腔被外延盖层回填。 外延区和外延盖层改善沟道区的电子迁移率，减少短沟道效应并降低寄生电阻。

公开(公告)号：US20110147816A1

公开(公告)日：2011-06-23

申请号：US12642342

申请日：2009-12-18

申请人： Dmitri E. Nikonov ,  George I. Bourianoff ,  Tahir Ghani

发明人： Dmitri E. Nikonov ,  George I. Bourianoff ,  Tahir Ghani

IPC分类号： H01L29/82 ,  H01L21/28

CPC分类号： H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/093 ,  G01R33/1284 ,  G11C11/161 ,  H01F10/133 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/307 ,  H01L27/22 ,  H01L27/228 ,  H01L43/12

摘要： Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.

摘要翻译： 描述了自旋扭矩磁集成电路及其装置。 自旋扭矩磁集成电路包括设置在基板上方的第一自由铁磁层。 非磁性层设置在第一自由铁磁层的上方。 包括多个写柱和多个读柱，每个柱设置在非磁性层之上并且包括固定的铁磁层。

公开(公告)号：US07226824B2

公开(公告)日：2007-06-05

申请号：US10918818

申请日：2004-08-13

申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

IPC分类号： H01L21/338

CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

公开(公告)号：US20060151832A1

公开(公告)日：2006-07-13

申请号：US11233854

申请日：2005-09-09

申请人： Anand Murthy ,  Robert Chau ,  Tahir Ghani

发明人： Anand Murthy ,  Robert Chau ,  Tahir Ghani

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US20050184311A1

公开(公告)日：2005-08-25

申请号：US11107141

申请日：2005-04-14

申请人： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

发明人： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。