公开(公告)号：US20060203938A1

公开(公告)日：2006-09-14

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US20060082478A1

公开(公告)日：2006-04-20

申请号：US11284498

申请日：2005-11-21

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： H03M9/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US20050007806A1

公开(公告)日：2005-01-13

申请号：US10910979

申请日：2004-08-03

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

摘要翻译： 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US20070115712A1

公开(公告)日：2007-05-24

申请号：US11654435

申请日：2007-01-16

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/06

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

摘要翻译： 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US20050007807A1

公开(公告)日：2005-01-13

申请号：US10910980

申请日：2004-08-03

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US20210240344A1

公开(公告)日：2021-08-05

申请号：US17162796

申请日：2021-01-29

申请人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

发明人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

IPC分类号： G06F3/06

摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

公开(公告)号：US20210200464A1

公开(公告)日：2021-07-01

申请号：US17136728

申请日：2020-12-29

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G06F3/06

摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

公开(公告)号：US09214449B2

公开(公告)日：2015-12-15

申请号：US13367026

申请日：2012-02-06

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G01R31/26 ,  H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  G11C29/02 ,  G11C29/00 ,  G11C5/04 ,  G11C29/32

CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C29/02 ,  G11C29/022 ,  G11C29/70 ,  G11C2029/3202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1531 ,  H01L2924/00

摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

摘要翻译： 一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为 检查连接中的缺陷并修复连接的缺陷。

公开(公告)号：US08712249B2

公开(公告)日：2014-04-29

申请号：US13080376

申请日：2011-04-05

申请人： Russel J. Baker ,  Brent Keeth

发明人： Russel J. Baker ,  Brent Keeth

IPC分类号： H04B10/00

CPC分类号： G11C11/4093 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/287 ,  G06F13/4234 ,  G11C11/42 ,  H04B10/802 ,  H04L12/40013 ,  H04Q11/0071 ,  Y02D10/14 ,  Y02D10/151

摘要： A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

摘要翻译： 公开了一种用于实现控制器和存储器件之间的电气隔离的光学链路。 光链路增加了电互连的抗噪声能力，并且允许存储器件被放置在距离处理器更远的位置，而不需要耗电的I / O缓冲器。

公开(公告)号：US20120246434A1

公开(公告)日：2012-09-27

申请号：US13489246

申请日：2012-06-05

申请人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

发明人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC分类号： G06F12/00

CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。