公开(公告)号：US06753260B1

公开(公告)日：2004-06-22

申请号：US09970787

申请日：2001-10-05

申请人： Lain-Jong Li ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Syun-Ming Jang ,  Jun-Lung Huang ,  Jeng-Cheng Liu

发明人： Lain-Jong Li ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Syun-Ming Jang ,  Jun-Lung Huang ,  Jeng-Cheng Liu

IPC分类号： H01L21311

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76834

摘要： A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.

公开(公告)号：US06677251B1

公开(公告)日：2004-01-13

申请号：US10207339

申请日：2002-07-29

申请人： Hsin-Hsien Lu ,  Aaron Song ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Hsin-Hsien Lu ,  Aaron Song ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2131

CPC分类号： H01L21/76826 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814

摘要： A method for forming a dielectric insulating layer with increased hydrophilicity for improving adhesion of an adjacently deposited material layer in semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing the dielectric insulating layer; and, subjecting the dielectric insulating layer including an exposed surface to a hydrophilicity increasing treatment including at least one of a dry plasma treatment and a wet process including contacting the exposed surface with a hydrophilicity increasing solution including a surfactant said wet process followed by a baking process to improve an adhesion of an adjacently deposited material layer.

摘要翻译： 一种用于形成具有增加的亲水性以提高相邻沉积材料层在半导体器件制造中的粘合性的介电绝缘层的方法，包括提供具有用于在其上形成介电绝缘层的工艺表面的半导体晶片; 沉积介电绝缘层; 并且使包含暴露表面的介电绝缘层经受包括干法等离子处理和湿法中的至少一种的亲水性增加处理，包括使暴露表面与包含表面活性剂的亲水性增加溶液接触，然后进行烘烤处理 以改善相邻沉积材料层的粘附性。

公开(公告)号：US6136680A

公开(公告)日：2000-10-24

申请号：US489498

申请日：2000-01-21

申请人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

发明人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.

摘要翻译： 一种形成互连的方法，包括以下步骤。 提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。 然后在电介质层上形成具有预定厚度的FSG层。 具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。 具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。 然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。 所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。 然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。 然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

公开(公告)号：US20060211240A1

公开(公告)日：2006-09-21

申请号：US11084494

申请日：2005-03-18

申请人： Chung Chi ,  Tien-I Bao ,  Syun-Ming Jang ,  Shou-Yi Chang

发明人： Chung Chi ,  Tien-I Bao ,  Syun-Ming Jang ,  Shou-Yi Chang

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/3122 ,  H01L21/02123 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3125 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/3212 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76835

摘要： A method for enhancing adhesion between adjacent dielectric layers, particularly in the formation of trenches and vias in the layers during the fabrication of semiconductor integrated circuits on wafer substrates. The method may include providing a via dielectric layer on a substrate above a metal conductive layer in the substrate, providing an adhesive layer on the via dielectric layer, providing a trench dielectric layer on the adhesive layer, etching a via in the via dielectric layer, etching a trench in the trench dielectric layer, filling the via and trench with a metal filling layer, and planarizing the filling layer. The adhesive layer between the via dielectric layer and the trench dielectric layer prevents CMP-induced peeling during the planarization step, and cracking of the layers during the package step.

摘要翻译： 一种用于增强相邻电介质层之间的粘附性的方法，特别是在晶片衬底上制造半导体集成电路期间在层中形成沟槽和通孔的方法。 该方法可以包括在衬底上的金属导电层上方的衬底上提供通孔电介质层，在通孔电介质层上提供粘合剂层，在粘合剂层上提供沟槽电介质层，蚀刻通孔电介质层中的通孔， 蚀刻沟槽电介质层中的沟槽，用金属填充层填充通孔和沟槽，并平坦化填充层。 通孔电介质层和沟槽电介质层之间的粘合剂层防止了在平坦化步骤期间的CMP引起的剥离以及在封装步骤期间层的破裂。

公开(公告)号：US07109119B2

公开(公告)日：2006-09-19

申请号：US10285021

申请日：2002-10-31

申请人： Tien-I Bao ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： An improved method of patterning photoresist is described that is resistant to poisoning from nearby nitrogen containing layers. An inert resin is used to fill a via in a damascene stack. Then a second stack comprised of a barrier layer, a BARC, and a photoresist are formed on the damascene stack. The barrier layer is preferably an i-line or Deep UV photoresist comprising a polymer with hydroxy groups that can attract nitrogen containing compounds and prevent them from diffusing into the photoresist and causing scum during the patterning step. The photoresist pattern is etch transferred through underlying layers to form a trench in the damascene stack. Optionally, the resin is replaced by the barrier layer which fills the via and forms a planar layer on the damascene stack. The barrier layer is independent of exposure wavelength and can be readily implemented into manufacturing and is extendable to future technologies.

摘要翻译： 描述了一种改进的图案化光刻胶方法，其耐受来自附近含氮层的中毒。 使用惰性树脂填充镶嵌层中的通孔。 然后在镶嵌层上形成由阻挡层，BARC和光致抗蚀剂组成的第二叠层。 阻挡层优选为i线或深UV光致抗蚀剂，其包含具有羟基的聚合物，其可以吸引含氮化合物并防止它们扩散到光致抗蚀剂中并在图案化步骤期间引起浮渣。 光致抗蚀剂图案被蚀刻转移通过下面的层以在镶嵌层中形成沟槽。 任选地，树脂被填充通孔的阻挡层代替，并在镶嵌层上形成平面层。 阻挡层独立于曝光波长，并且可以容易地实现到制造中，并且可扩展到未来的技术。

公开(公告)号：US06455417B1

公开(公告)日：2002-09-24

申请号：US09899419

申请日：2001-07-05

申请人： Tien-I Bao ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/3212 ,  H01L21/76801 ,  H01L21/76807

摘要： Within a damascene method for forming a microelectronic fabrication, there is employed a first etch stop/liner layer formed upon a substrate, wherein the first etch stop/liner layer comprises a first layer formed upon the substrate and formed of a carbon doped silicon nitride material and a second layer formed upon the first layer and formed of a carbon doped silicon oxide material. The first etch stop/liner layer formed in accord with the above materials selections provides for attenuated oxidation of the substrate and attenuated residue formation of a photoresist layer coated, photo exposed and developed in contact with the first etch stop/liner layer.

摘要翻译： 在用于形成微电子制造的镶嵌方法中，采用形成在衬底上的第一蚀刻停止/衬垫层，其中第一蚀刻停止层/衬层包括形成在衬底上并由碳掺杂的氮化硅材料形成的第一层 以及形成在第一层上并由碳掺杂的氧化硅材料形成的第二层。 根据上述材料选择形成的第一蚀刻停止/衬里层提供了衬底的衰减氧化，并且与第一蚀刻停止/衬底层接触地涂覆，曝光和显影的光致抗蚀剂层的残留物形成减弱。

公开(公告)号：US06181013B2

公开(公告)日：2001-01-30

申请号：US09524521

申请日：2000-03-13

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2348

CPC分类号： H01L21/76867 ,  H01L21/7684 ,  H01L21/76849

摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.

摘要翻译： 在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。 在包括导电基板的暴露表面和电介质层的暴露的侧壁的电介质层上形成阻挡层。 在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。 通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。 通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。 从铜化合物的表面和阻挡层的表面蚀刻掉材料以通过蚀刻到电介质顶部水平来平坦化铜化合物，留下覆盖较窄孔中的铜导体的铜钝化化合物的薄层。

公开(公告)号：US06046108A

公开(公告)日：2000-04-04

申请号：US344402

申请日：1999-06-25

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76867 ,  H01L21/7684 ,  H01L21/76849

摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planiarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.

摘要翻译： 在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。 在包括导电基底的暴露表面和电介质层暴露的侧壁的电介质层上形成阻挡层。 在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。 通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。 通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。 从铜化合物的表面和阻挡层的表面蚀刻掉材料，以通过蚀刻到电介质顶层来平面化铜化合物，留下在较窄的孔中覆盖铜导体的铜钝化化合物的薄层。

公开(公告)号：US07223692B2

公开(公告)日：2007-05-29

申请号：US10836297

申请日：2004-04-30

申请人： Keng-Chu Lin ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Keng-Chu Lin ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L21/447 ,  H01L21/4763

CPC分类号： H01L21/76826 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping layer on the exposed surface; providing a treatment on the first capping layer to increase interface adhesion between the capping layer and the dielectric insulating layer; and, forming a second capping layer on the first capping layer.

摘要翻译： 一种包括具有改进的层间粘合性的铜互连的多层半导体器件及其形成方法，所述方法包括提供半导体衬底，所述半导体衬底包括包含铜的介电绝缘层，所述电介质绝缘层将所述介电绝缘层和包含暴露表面的含铜互连互连; 在所述暴露表面上形成第一覆盖层; 在所述第一盖层上提供处理以增加所述封盖层和所述介电绝缘层之间的界面粘附; 并且在所述第一覆盖层上形成第二覆盖层。

公开(公告)号：US20060278870A1

公开(公告)日：2006-12-14

申请号：US11497595

申请日：2006-08-02

申请人： Tien-I Bao ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L29/08

CPC分类号： H01L21/31116 ,  H01L21/76807 ,  H01L21/76834 ,  H01L2221/1089

摘要： A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.

摘要翻译： 一种用于处理半导体结构的方法包括以下步骤：用薄的阻挡层覆盖限定金属化层的半导体结构的顶表面，在薄的停止层上形成电介质层，其中介电层限定至少一个区域， 暴露薄的止挡层，并且使用基本上不含氧的蚀刻剂气体去除暴露的薄止挡层以暴露金属化层的顶表面，使得金属化层基本上没有损坏。