公开(公告)号：US5581567A

公开(公告)日：1996-12-03

申请号：US401297

申请日：1995-03-09

申请人： Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Willem B. van der Hoeven

发明人： Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Willem B. van der Hoeven

IPC分类号： G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/1008

摘要： A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.

摘要翻译： 一种提供额外数据位而不占用存储容量的存储器系统。 从存储器中取出第一个数据字，并进行纠正以消除任何单位错误。 然后取出第二数据字（其是被校正的第一数据字的子集），并且为第二数据字生成新的数据校正位（奇偶校验位或ECC校验位）。 输出第二数据字和新产生的数据校正位。 该结构通过更大的数据输出和相对于数据输出的较小的存储容量来摊销系统内数据校正的费用。

公开(公告)号：US5533036A

公开(公告)日：1996-07-02

申请号：US486628

申请日：1995-06-07

申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

摘要翻译： 在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个存储器单元都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正能力的装置来增强存储器可靠性 例如，响应于在一个存储器单元中出现不可校正的错误。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

公开(公告)号：US5031151A

公开(公告)日：1991-07-09

申请号：US600944

申请日：1990-10-22

申请人： John A. Fifield ,  Howard L. Kalter ,  Christopher P. Miller ,  Steven W. Thomashot

发明人： John A. Fifield ,  Howard L. Kalter ,  Christopher P. Miller ,  Steven W. Thomashot

IPC分类号： G11C29/00

CPC分类号： G11C29/84

摘要： A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.

摘要翻译： 描述了在不影响访问时间的情况下实现字线冗余的半导体存储器件。 冗余解码器电路产生禁止产生正常字线信号的字线驱动禁止信号。 取消选择也取消选择通常访问的参考单元，要求冗余单元提供自己的参考信号。 最后一个要求是通过利用双电池来实现冗余存储器。 将冗余存储器单元放置在位线隔离器的感测节点侧使得能够有效地加倍可用于正常存储器的多个子阵列中的每一个的冗余单元。

公开(公告)号：US6087199A

公开(公告)日：2000-07-11

申请号：US18737

申请日：1998-02-04

申请人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

发明人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/13 ,  H01L25/065 ,  H01L29/06 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/76838 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/83141 ,  H01L2224/97 ,  H01L29/0657 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/3025

摘要： A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m

摘要翻译： 一种用于制造集成电路封装或布置的方法包括提供具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。 设置芯片使得相邻芯片的顶面基本上位于大于0.0μm的距离上的平面中。 载体的布置和尺寸使得相邻的芯片由间隙G分隔开，或间隔在1μm×100μm的范围内。 在顶面和间隙上设有金属互连。 优选地，互连在间隙上具有逐渐的斜率。

公开(公告)号：US6044024A

公开(公告)日：2000-03-28

申请号：US7433

申请日：1998-01-14

申请人： John E. Barth ,  Jeffrey H. Dreibelbis ,  Howard L. Kalter

发明人： John E. Barth ,  Jeffrey H. Dreibelbis ,  Howard L. Kalter

IPC分类号： G11C11/417 ,  G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G11C16/04 ,  G11C7/02

CPC分类号： G11C7/10

摘要： An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.

摘要翻译： 嵌入式存储器宏器件包括存储器系统和构造在公共半导体衬底上的逻辑电路。 存储器系统和逻辑电路经由系统数据互锁信号通过握手程序进行通信。 在读周期中，当存储器系统数据输出的数据有效时，存储器系统使用系统数据互锁信号来告知逻辑电路。 在优选实施例中，在写入周期期间，当数据被成功写入时，存储器系统使用系统数据互锁信号来告诉逻辑电路。 逻辑电路需要等到系统数据互锁信号允许它继续进行。 然后，它将信号通知存储系统以复位系统数据互锁信号，并可以立即启动新的读或写周期。

公开(公告)号：US5241500A

公开(公告)日：1993-08-31

申请号：US922597

申请日：1992-07-29

申请人： John E. Barth, Jr. ,  Howard L. Kalter

发明人： John E. Barth, Jr. ,  Howard L. Kalter

IPC分类号： G11C11/401 ,  G11C7/20 ,  G11C8/12 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/50

CPC分类号： G11C29/50 ,  G11C29/14 ,  G11C29/34 ,  G11C7/20 ,  G11C8/12 ,  G11C16/04

摘要： A method is provided for flash writing to multiple cells of a memory array. Initially, a first set of word lines, each of which controls connection of a memory cell of a first set of memory cells to a first bit line of a bit line pair, is turned on. The voltage between the two bit lines of the bit line pair is then equalized so that the charge on the first bit line of the bit line pair is higher than the charge on the second bit line of the bit line pair. Next, a sense amplifier attached to the bit line pair is turned on to sense a difference in charge between the bit line pair and to charge the first set of memory cells. Then a second set of word lines, each of which controls connection of a memory cell of a second set of memory cells to the second bit line is turned on. Finally, the word lines previously turned on are shut off and then the sense amplifier is shut off. Additionally, an apparatus is provided which allows for: turning on multiple word lines at one time, keeping an equalization means on until after at least one set of word lines have gone on, and controlling the operation of the sense amplifier to turn on and shut off at appropriate times.

摘要翻译： 提供了一种用于闪存写入存储器阵列的多个单元的方法。 最初，将第一组字线控制第一组存储器单元的存储单元与位线对的第一位线的连接。 然后，位线对的两个位线之间的电压被均衡，使得位线对的第一位线上的电荷高于位线对的第二位线上的电荷。 接下来，连接到位线对的读出放大器导通，以感测位线对之间的电荷差，并对第一组存储器单元充电。 然后，第二组字线，其中的每一个控制第二组存储器单元的存储单元与第二位线的连接。 最后，关闭以前打开的字线，然后关闭读出放大器。 此外，提供了一种装置，其允许：一次打开多个字线，保持均衡装置开启，直到在至少一组字线已经过去之后，并且控制读出放大器的操作以导通和关闭 在适当的时候关闭。

公开(公告)号：US5134616A

公开(公告)日：1992-07-28

申请号：US479145

申请日：1990-02-13

申请人： John E. Barth, Jr. ,  Charles E. Drake ,  John A. Fifield ,  William P. Hovis ,  Howard L. Kalter ,  Scott C. Lewis ,  Daniel J. Nickel ,  Charles H. Stapper ,  James A. Yankosky

发明人： John E. Barth, Jr. ,  Charles E. Drake ,  John A. Fifield ,  William P. Hovis ,  Howard L. Kalter ,  Scott C. Lewis ,  Daniel J. Nickel ,  Charles H. Stapper ,  James A. Yankosky

IPC分类号： G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42

CPC分类号： G11C29/84 ,  G06F11/1008

摘要： A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：US5015880A

公开(公告)日：1991-05-14

申请号：US419341

申请日：1989-10-10

申请人： Charles E. Drake ,  Howard L. Kalter ,  Scott C. Lewis

发明人： Charles E. Drake ,  Howard L. Kalter ,  Scott C. Lewis

IPC分类号： H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/00361 ,  H03K19/01721

摘要： A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：US5010524A

公开(公告)日：1991-04-23

申请号：US340962

申请日：1989-04-20

申请人： John A. Fifield ,  Howard L. Kalter

发明人： John A. Fifield ,  Howard L. Kalter

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C7/18

摘要： This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

公开(公告)号：US06730529B1

公开(公告)日：2004-05-04

申请号：US09236183

申请日：1999-01-25

申请人： Howard L. Kalter ,  H. Bernhard Pogge ,  George S. Prokop ,  Donald L. Wheater

发明人： Howard L. Kalter ,  H. Bernhard Pogge ,  George S. Prokop ,  Donald L. Wheater

IPC分类号： G01R3126

CPC分类号： H01L22/32 ,  G01R31/2884

摘要： Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.

摘要翻译： 大面积芯片功能在制造过程的中间级别进行测试。 实现了在芯片上沉积绝缘体材料层的工艺顺序。 然后将该层处理成选择性地打开将用于芯片级测试的现有通孔上的区域。 其他通孔仍然用绝缘体覆盖。 然后将牺牲金属水平沉积在绝缘体层上并图案化以产生连接到暴露的通孔的足够大的测试焊盘区域。 在测试之后，该金属层和覆盖另一埋孔的绝缘体层被重新建立完整的通孔。 作为这个基本测试过程的延伸，测试电路可以在将芯片与半导体晶片上的其他芯片分开的切口区域中围绕或测试芯片周围形成。 与测试电路的连接在绝缘体层上具有牺牲金属层。 测试后去除牺牲金属层和绝缘体层。 在线路处理后端完成之后分离芯片的过程中，划线测试电路。