公开(公告)号：US20200220008A1

公开(公告)日：2020-07-09

申请号：US16819771

申请日：2020-03-16

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Yasuhiro EBIHARA ,  Masahiro SUGIMOTO ,  Yusuke YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

公开(公告)号：US20190386094A1

公开(公告)日：2019-12-19

申请号：US16304783

申请日：2017-06-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Shuhei MITANI ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.

公开(公告)号：US20190334030A1

公开(公告)日：2019-10-31

申请号：US16505760

申请日：2019-07-09

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Atsuya AKIBA ,  Sachiko AOI ,  Katsumi SUZUKI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16

Abstract: A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.

公开(公告)号：US20190019680A1

公开(公告)日：2019-01-17

申请号：US16070061

申请日：2017-01-12

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Atsuya AKIBA ,  Katsumi SUZUKI ,  Sachiko AOI

IPC: H01L21/266 ,  H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

Abstract: A compound semiconductor device includes a semiconductor substrate having a ground layer of a first conductivity type made of a compound semiconductor, a first conductivity type region formed at a corner portion of a bottom of a deep trench formed to the ground layer, and a deep layer of a second conductivity type formed in the deep trench so as to cover the first conductivity type region. A cross section of the first conductivity type region is a triangular shape or a rounded triangular shape in which a portion of the first conductivity type region being in contact with the deep layer is recessed to have a curved surface.

公开(公告)号：US20170012108A1

公开(公告)日：2017-01-12

申请号：US15113475

申请日：2015-01-14

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Jun SAKAKIBARA ,  Nozomu AKAGI ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Katsumi SUZUKI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L23/544 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/66068 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/2015 ,  H01L21/2033 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7831 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.

Abstract translation: 在制造半导体器件的方法中，当形成第二导电型杂质层以在第一凹部中提供具有第二导电类型的深层并且在漂移层的表面上提供具有第二导电类型的沟道层 在与第一凹部的中心位置对应的第二导电型杂质层的一部分的表面上形成由凹部设置的接触沟槽的生长条件进行外延生长，并且接触区域由 在接触沟槽的底部离子注入第二导电型杂质。

公开(公告)号：US20150333127A1

公开(公告)日：2015-11-19

申请号：US14652483

申请日：2013-12-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomoo MORINO ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Akitaka SOENO ,  Yukihiko WATANABE

IPC: H01L29/16 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/761 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0642 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7815

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract translation: 碳化硅半导体器件包括：元件隔离层和电场弛豫层。 元件隔离层从基区的表面配置为比基区更深，位于主单元区域和感测单元区域之间，并且将主单元区域与感测单元区域隔离。 电场弛豫层从基底区域的底部排列成比元件隔离层更深。 电场弛豫层被分成主单元区域部分和感测单元区域部分。 元件隔离层的至少一部分布置在电场弛豫层的分割部分的内部。

公开(公告)号：US20240079492A1

公开(公告)日：2024-03-07

申请号：US18506290

申请日：2023-11-10

Applicant: DENSO CORPORATION

Inventor： Atsuya AKIBA ,  Yuichi TAKEUCHI ,  Kazuki ARAKAWA ,  Yusuke HAYAMA ,  Yasushi URAKAMI ,  Shinichiro MIYAHARA ,  Tomoo MORINO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608

Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

公开(公告)号：US20220102485A1

公开(公告)日：2022-03-31

申请号：US17546248

申请日：2021-12-09

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA ,  Yuichi TAKEUCHI ,  Yukihiko WATANABE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

公开(公告)号：US20200161467A1

公开(公告)日：2020-05-21

申请号：US16729733

申请日：2019-12-30

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Shuhei MITANI ,  Yasuhiro EBIHARA ,  Yusuke YAMASHITA ,  Tadashi MISUMI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

公开(公告)号：US20190386131A1

公开(公告)日：2019-12-19

申请号：US16304752

申请日：2017-06-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Katsumi SUZUKI ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/04 ,  H01L21/761 ,  H01L29/66

Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.