公开(公告)号：US07892940B2

公开(公告)日：2011-02-22

申请号：US11851123

申请日：2007-09-06

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US07327033B2

公开(公告)日：2008-02-05

申请号：US10710828

申请日：2004-08-05

申请人： Daniel C. Edelstein ,  Edward C. Cooney, III ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Edward C. Cooney, III ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US06838355B1

公开(公告)日：2005-01-04

申请号：US10604602

申请日：2003-08-04

申请人： Anthony K. Stamper ,  Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Lee M. Nicholson

发明人： Anthony K. Stamper ,  Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Lee M. Nicholson

IPC分类号： H01L21/31 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wiring structure which contains a dielectric material having relatively high dielectric constant (i.e., 4.0 or higher). The damascene structure comprises the higher dielectric constant material immediately adjacent to the metal interconnects, thus benefiting from the mechanical characteristics of these materials, while incorporating the lower dielectric constant material in other areas of the interconnect level.

摘要翻译： 公开的形成后端（BEOL）互连结构的方法。 该方法和结果包括低k电介质材料的回蚀。 具体地说，将低介电常数材料整合到双或单镶嵌布线结构中，该结构包含介电常数（即4.0或更高）的介电材料。 镶嵌结构包括紧邻金属互连件的较高介电常数材料，从而受益于这些材料的机械特性，同时将较低介电常数材料结合在互连级别的其他区域。

公开(公告)号：US08927869B2

公开(公告)日：2015-01-06

申请号：US13444343

申请日：2012-04-11

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H05K1/00

CPC分类号： H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

摘要： Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

摘要翻译： 公开了使用有机绝缘材料的引线键合半导体结构和制造方法。 该方法包括在有机绝缘体层中形成金属布线层。 该方法还包括在有机绝缘体层上形成保护层。 该方法还包括在金属布线层上的有机绝缘体层中形成通孔。 该方法还包括在通孔中和保护层上沉积金属层。 该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。

公开(公告)号：US20130200521A1

公开(公告)日：2013-08-08

申请号：US13367895

申请日：2012-02-07

申请人： Hanyi Ding ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Alvin J. Joseph ,  Anthony K. Stamper ,  Timothy D. Sullivan

发明人： Hanyi Ding ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Alvin J. Joseph ,  Anthony K. Stamper ,  Timothy D. Sullivan

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.

摘要翻译： 后端（BEOL）布线结构和电感器，BEOL布线结构和电感器的制造方法以及BEOL布线结构或电感器的设计结构。 形成可以是沟槽或导线的特征，其包括与电介质层的顶表面相交的侧壁。 表面层形成在特征的侧壁上。 表面层由导体构成，其厚度被选择为提供用于传导高频信号的低电阻路径。

公开(公告)号：US08709855B2

公开(公告)日：2014-04-29

申请号：US12133379

申请日：2008-06-05

申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L21/00

CPC分类号： H01L23/552 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。

公开(公告)号：US20090303366A1

公开(公告)日：2009-12-10

申请号：US12133380

申请日：2008-06-05

申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H04N5/335

CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643

摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。

公开(公告)号：US08900964B2

公开(公告)日：2014-12-02

申请号：US13367895

申请日：2012-02-07

申请人： Hanyi Ding ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Alvin J. Joseph ,  Anthony K. Stamper ,  Timothy D. Sullivan

发明人： Hanyi Ding ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Alvin J. Joseph ,  Anthony K. Stamper ,  Timothy D. Sullivan

IPC分类号： H01L21/20 ,  H01L27/08

CPC分类号： H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.

摘要翻译： 后端（BEOL）布线结构和电感器，BEOL布线结构和电感器的制造方法以及BEOL布线结构或电感器的设计结构。 形成可以是沟槽或导线的特征，其包括与电介质层的顶表面相交的侧壁。 表面层形成在特征的侧壁上。 表面层由导体构成，其厚度被选择为提供用于传导高频信号的低电阻路径。

公开(公告)号：US08158988B2

公开(公告)日：2012-04-17

申请号：US12133380

申请日：2008-06-05

申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L27/15 ,  H01L29/267 ,  H01L31/12 ,  H01L33/00

CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643

摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.