公开(公告)号：US20170309628A1

公开(公告)日：2017-10-26

申请号：US15642507

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

公开(公告)号：US20170117322A1

公开(公告)日：2017-04-27

申请号：US14918736

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

公开(公告)号：US09460955B2

公开(公告)日：2016-10-04

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。

公开(公告)号：US09312189B2

公开(公告)日：2016-04-12

申请号：US14244651

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/425 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括通过执行激光退火工艺来退火邻近p沟道栅叠层的半导体衬底中的卤注入区和延伸注入区。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US20150145000A1

公开(公告)日：2015-05-28

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。

公开(公告)号：US20150076618A1

公开(公告)日：2015-03-19

申请号：US14031361

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract translation: 为集成电路提供了方法和装置。 该方法包括在衬底上形成波纹掩模，并在衬底上形成通道波纹。 将波纹掩模从基板上移除，并且在衬底上形成覆盖通道波纹的栅极绝缘体。 栅极形成在通道栅极绝缘体上方。

公开(公告)号：US08951877B2

公开(公告)日：2015-02-10

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20140361385A1

公开(公告)日：2014-12-11

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US09941348B2

公开(公告)日：2018-04-10

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/762

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US09741625B2

公开(公告)日：2017-08-22

申请号：US14844163

申请日：2015-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Pei-Yu Chou

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/31055 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092

Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.