公开(公告)号：US09087743B2

公开(公告)日：2015-07-21

申请号：US14084899

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/4763 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.

Abstract translation: 本发明的实施例提供一种半导体结构，其包括具有与多个鳍状物直接物理接触的外延半导体区域的finFET，其中外延半导体区域穿过绝缘体层并与半导体衬底直接物理接触。 finFET的栅极设置在诸如掩埋氧化物层的绝缘体层上。 还包括形成半导体结构的方法。

公开(公告)号：US09034737B2

公开(公告)日：2015-05-19

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。

公开(公告)号：US10003302B2

公开(公告)日：2018-06-19

申请号：US15496049

申请日：2017-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L29/739 ,  H03C3/14 ,  H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H03D7/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.

公开(公告)号：US09601578B2

公开(公告)日：2017-03-21

申请号：US14511769

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu ,  Vara Govindeswara Reddy Vakada

IPC: H01L29/66 ,  H01L27/108 ,  H01L21/70 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/1095 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/66545 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7835

Abstract: A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure.

公开(公告)号：US09406752B2

公开(公告)日：2016-08-02

申请号：US14676912

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Jianwei Peng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Francis Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L21/265 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US09397191B2

公开(公告)日：2016-07-19

申请号：US14922308

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/08 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region.

Abstract translation: 在半导体衬底中形成隔离区域以横向限定并电隔离器件区域，并且在器件区域中形成第一和第二横向相邻阱区域。 在器件区域上方形成栅极结构，使得第一阱区域延伸到整个栅极结构的下方，并且形成在第一阱区域和第二阱区域之间的阱区域界面从栅极结构的漏极侧边缘横向偏移。 源极和漏极区域形成在器件区域中，使得源极区域从栅极结构的源极侧边缘横向延伸并跨越第一阱区域的第一部分延伸到隔离区域的第一内部边缘，并且漏极区域 从排水侧边缘横向延伸并穿过第一井区域的第二部分。

公开(公告)号：US20150348830A1

公开(公告)日：2015-12-03

申请号：US14824361

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

公开(公告)号：US09142640B1

公开(公告)日：2015-09-22

申请号：US14306864

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiaodong Yang ,  Yanxiang Liu ,  Jin Ping Liu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A non-planar transistor is fabricated with dummy or sacrificial epitaxy and a structure for subsequent replacement or final epitaxy containment is created around the sacrificial epitaxy. The dummy epitaxy is then removed and replaced with the replacement epitaxy. The containment structure allows for uniform growth of the replacement epitaxy and prevents merger. Where n-type and p-type structures are present, the replacement epitaxy process is performed for each type, while protecting the other type with a mask. Optionally, one of the replacement epitaxies, i.e., the one for n-type or p-type, may be used as the dummy epitaxy, resulting in the need for only one mask.

Abstract translation: 用虚拟或牺牲外延制造非平面晶体管，并且在牺牲外延周围产生用于后续替换或最终外延容纳的结构。 然后去除虚拟外延并用替换外延代替。 容纳结构允许替代外延的均匀生长并且防止合并。 在存在n型和p型结构的情况下，对于每种类型进行替换外延工艺，同时用掩模保护另一种类型。 任选地，替代的外延（即，用于n型或p型的）中的一种可以用作虚拟外延，导致仅需要一个掩模。

公开(公告)号：US09142316B2

公开(公告)日：2015-09-22

申请号：US14017417

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi ,  Anurag Mittal

IPC: G11C17/00 ,  G11C17/12 ,  G11C17/16 ,  H01L21/762 ,  H01L27/112 ,  H01L23/525

CPC classification number: G11C17/12 ,  G11C17/16 ,  G11C17/18 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates.

Abstract translation: 提供了没有附加选择器的OTP反熔丝存储器阵列和制造方法。 实施例包括在衬底中形成第一极性的阱，在每个阱中形成第一极性的位线，以及在每个位线之间形成多个金属栅极，其中在金属栅极之间不形成源极/漏极区。

公开(公告)号：US09007803B2

公开(公告)日：2015-04-14

申请号：US13937962

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: G11C17/00 ,  H01L27/112 ,  H01L21/768 ,  G11C17/16

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L21/76816 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area.

Abstract translation: 为具有可编程电气连接的集成电路提供了方法和装置。 该装置包括具有通过非活动区域的存储器线路的无效区域。 存储线包括可编程层。 层间电介质位于存储器线路和无源区域之上，并且延伸部件延伸穿过层间电介质。 延伸构件在非活动区域上方的点处电连接到存储器线路的可编程层。