公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09281249B2

公开(公告)日：2016-03-08

申请号：US14155504

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alok Vaid ,  Abner Bello ,  Sipeng Gu ,  Lokesh Subramany ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/66 ,  G01B11/02 ,  G01B11/06 ,  G03F7/20 ,  G01N21/21

CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。

公开(公告)号：US09129905B2

公开(公告)日：2015-09-08

申请号：US14070624

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Lokesh Subramany ,  Alok Vaid ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/3083 ,  H01L21/3086 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Abstract translation: 公开了一种用于提供与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除，例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模，并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去，允许在其中形成一组翅片，而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

公开(公告)号：US09121890B2

公开(公告)日：2015-09-01

申请号：US14067204

申请日：2013-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L21/311 ,  H01L21/302 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract translation: 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US08969932B2

公开(公告)日：2015-03-03

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20140159126A1

公开(公告)日：2014-06-12

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。