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公开(公告)号：US20150357434A1
公开(公告)日：2015-12-10
申请号：US14827510
申请日：2015-08-17
Inventor： Linus Jang , Sivananda K. Kanakasabapathy , Sanjay C. Mehta , Soon-Cheon Seo , Raghavasimhan Sreenivasan
IPC: H01L29/66 , H01L21/3065 , H01L21/283
CPC classification number: H01L29/66545 , H01L21/283 , H01L21/3065 , H01L21/31144 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6656 , H01L29/66795
Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.
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公开(公告)号：US20150214331A1
公开(公告)日：2015-07-30
申请号：US14168112
申请日：2014-01-30
Inventor： Linus Jang , Sivananda K. Kanakasabapathy , Sanjay C. Mehta , Soon-Cheon Seo , Raghavasimhan Sreenivasan
IPC: H01L29/66 , H01L21/8234
CPC classification number: H01L29/66545 , H01L21/02164 , H01L21/2018 , H01L21/28238 , H01L21/3065 , H01L21/31053 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/41783 , H01L29/41791 , H01L29/4966 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/66795 , H01L29/7851 , H01L29/7855 , H01L2029/7858
Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.
Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在布置在散热片上的蚀刻停止层上形成多个栅极形成层。 多个栅极形成层包括由电介质材料形成的虚拟栅极层。 图案化多个栅极形成层以在蚀刻停止层上形成多个虚拟栅极元件。 每个伪栅极元件由电介质材料形成。 蚀刻形成在虚拟栅极元件上的间隔层，以在虚拟栅极元件的每个侧壁上形成间隔物。 位于每个伪栅元件之间的蚀刻停止层的一部分被蚀刻以暴露半导体鳍片的一部分。 半导体材料从半导体鳍片的暴露部分外延生长以形成源极/漏极区域。
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公开(公告)号：US10128352B2
公开(公告)日：2018-11-13
申请号：US15432372
申请日：2017-02-14
Inventor： Su Chen Fan , Andre P. Labonte , Lars W. Liebmann , Sanjay C. Mehta
IPC: H01L23/535 , H01L29/66 , H01L21/768 , H01L21/027 , H01L27/11 , H01L21/311 , H01L23/522 , H01L23/528
Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
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公开(公告)号：US09735054B2
公开(公告)日：2017-08-15
申请号：US15175776
申请日：2016-06-07
Inventor： Su Chen Fan , Andre P. Labonte , Lars W. Liebmann , Sanjay C. Mehta
IPC: H01L21/768 , H01L21/027 , H01L29/66 , H01L23/535 , H01L27/11 , H01L21/311
CPC classification number: H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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公开(公告)号：US20170170070A1
公开(公告)日：2017-06-15
申请号：US15443523
申请日：2017-02-27
Inventor： Su Chen Fan , Andre P. Labonte , Lars W. Liebmann , Sanjay C. Mehta
IPC: H01L21/768 , H01L21/311 , H01L21/027 , H01L29/66
CPC classification number: H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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Patent Agency Ranking
公开(公告)号：US09653573B2
公开(公告)日：2017-05-16
申请号：US14827510
申请日：2015-08-17
Inventor： Linus Jang , Sivananda K. Kanakasabapathy , Sanjay C. Mehta , Soon-Cheon Seo , Raghavasimhan Sreenivasan
IPC: H01L29/66 , H01L21/8234 , H01L21/283 , H01L21/3065 , H01L21/311
CPC classification number: H01L29/66545 , H01L21/283 , H01L21/3065 , H01L21/31144 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6656 , H01L29/66795
Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.
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公开(公告)号：US09640514B1
公开(公告)日：2017-05-02
申请号：US15084004
申请日：2016-03-29
Applicant: GLOBALFOUNDRIES INC.
Inventor： Wei Lin , Troy L. Graves-Abe , Donald F. Canaperi , Spyridon Skordas , Matthew T. Shoudy , Binglin Miao , Raghuveer R. Patlolla , Sanjay C. Mehta
IPC: H01L25/065 , H01L21/762 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/76251 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/50 , H01L2224/29084 , H01L2224/29187 , H01L2224/32145 , H01L2224/83031 , H01L2224/83193 , H01L2224/832 , H01L2224/83896 , H01L2924/01005 , H01L2924/01007 , H01L2924/01008 , H01L2924/01014 , H01L2924/0503 , H01L2924/05442 , H01L2924/059 , H01L2924/20109 , H01L2924/206 , H01L2924/2064
Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.
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公开(公告)号：US09627257B2
公开(公告)日：2017-04-18
申请号：US15175835
申请日：2016-06-07
Inventor： Su Chen Fan , Andre P. Labonte , Lars W. Liebmann , Sanjay C. Mehta
IPC: H01L21/768 , H01L29/66 , H01L27/11 , H01L23/535
CPC classification number: H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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公开(公告)号：US09576954B1
公开(公告)日：2017-02-21
申请号：US14862258
申请日：2015-09-23
IPC: H01L27/092 , H01L29/772 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L21/3105 , H01L21/311 , H01L21/762 , H01L29/06
CPC classification number: H01L29/4983 , H01L21/0214 , H01L21/02167 , H01L21/0217 , H01L21/0332 , H01L21/31053 , H01L21/31116 , H01L21/31144 , H01L21/76205 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823864 , H01L27/0886 , H01L29/0649 , H01L29/42368 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66795
Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.
Abstract translation: 在栅极之间填充沟槽的方法包括在衬底上形成第一和第二虚拟栅极，第一和第二伪栅极包括牺牲栅极材料和硬掩模层; 沿着第一伪栅极的侧壁形成第一栅极间隔物，沿着第二虚拟栅极的侧壁形成第二栅极间隔物; 执行外延生长工艺以在第一和第二虚拟栅极之间的衬底上形成源极/漏极; 在第一和第二伪栅极和源极/漏极上设置保形衬垫; 在第一和第二伪栅极之间的保形衬垫上设置氧化物; 将氧化物凹陷到低于第一和第二伪栅极的硬掩模层的水平以形成凹陷氧化物; 以及在第一伪栅极和第二虚拟栅极之间的凹陷氧化物上沉积间隔物材料。
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公开(公告)号：US20170047254A1
公开(公告)日：2017-02-16
申请号：US15175835
申请日：2016-06-07
Inventor： Su Chen Fan , Andre P. Labonte , Lars W. Liebmann , Sanjay C. Mehta
IPC: H01L21/768 , H01L27/11 , H01L23/535 , H01L29/66
CPC classification number: H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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