公开(公告)号：US20170186845A1

公开(公告)日：2017-06-29

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US20210057462A1

公开(公告)日：2021-02-25

申请号：US16544074

申请日：2019-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L27/144 ,  H01L29/04 ,  H01L29/165 ,  H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18

Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

公开(公告)号：US10832940B2

公开(公告)日：2020-11-10

申请号：US16218868

申请日：2018-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10720494B2

公开(公告)日：2020-07-21

申请号：US15876530

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Cameron Luce ,  Pernell Dongmo

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/76 ,  H01L21/02 ,  H01L21/764 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/308 ,  H01L21/768

Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

公开(公告)号：US10429582B1

公开(公告)日：2019-10-01

申请号：US15968997

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/26 ,  G02B6/122 ,  G02B6/136 ,  G02B6/125 ,  G02B6/124 ,  G02B6/12

Abstract: Waveguide-to-waveguide couplers, systems that include waveguide-to-waveguide couplers, and methods of fabricating waveguide-to-waveguide couplers. A first waveguide is coupled to a first waveguide taper, and a second waveguide is coupled to a second waveguide taper. The first waveguide and the first waveguide taper are comprised of silicon, and the second waveguide and the second waveguide taper are comprised of silicon nitride. The second waveguide and the second waveguide taper are arranged in a vertical direction over the first waveguide and the first waveguide taper.

公开(公告)号：US10163955B2

公开(公告)日：2018-12-25

申请号：US15671223

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L31/101 ,  G02B6/42 ,  H01L31/0232 ,  H01L21/762

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US20180350659A1

公开(公告)日：2018-12-06

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/0262 ,  H01L21/76235 ,  H01L21/7624

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

公开(公告)号：US20180204926A1

公开(公告)日：2018-07-19

申请号：US15921715

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US09978849B2

公开(公告)日：2018-05-22

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US20170358619A1

公开(公告)日：2017-12-14

申请号：US15671223

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L31/0232 ,  H01L21/762

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.