公开(公告)号：US09236258B2

公开(公告)日：2016-01-12

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150340457A1

公开(公告)日：2015-11-26

申请号：US14283404

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ajey Poovannummoottil Jacob

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.

Abstract translation: 本文公开的一种说明性方法包括在晶体管器件的源极/漏极区域中形成第一外延半导体材料，第一外延半导体材料在其上表面具有第一横向宽度，形成第二外延半导体材料 在所述第一外延半导体材料上以及所述器件的所述侧壁间隔物中的至少一部分栅极帽层或所述侧壁间隔物中的至少一部分，其中所述第二外延半导体材料在其上表面处具有大于 第一横向宽度，并且在第二外延半导体材料的上表面上形成金属硅化物区域。

公开(公告)号：US20150340238A1

公开(公告)日：2015-11-26

申请号：US14811987

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/308 ,  H01L21/8234

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US20150318176A1

公开(公告)日：2015-11-05

申请号：US14267154

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

IPC: H01L21/265 ,  H01L29/165 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L21/26513 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6681 ,  H01L29/7849

Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract translation: 公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在翅片沟槽中形成基本上无缺陷的半导体材料层，在第二层半导体材料上形成第二层半导体材料 形成第一半导体材料层的上表面，在第一半导体材料层和衬底之间的界面处形成注入区域，执行退火工艺以在至少第一半导体材料层中形成缺陷，形成 在所述第二半导体材料层上的第三层半导体材料，在所述第三半导体材料层上形成沟道半导体材料层，以及围绕所述沟道半导体材料的至少一部分形成栅极结构。

公开(公告)号：US20150311081A1

公开(公告)日：2015-10-29

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150279959A1

公开(公告)日：2015-10-01

申请号：US14242529

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66

CPC classification number: H01L21/823431

Abstract: One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.

Abstract translation: 本文中公开的一种说明性方法包括在形成牺牲材料区域之后，在要被去除的翅片的部分将被定位的位置处在半导体衬底中形成牺牲材料的区域，执行至少一个 第一蚀刻工艺以形成限定翅片的多个翅片形成沟槽，其中鳍片的至少一部分由牺牲材料构成，并且执行至少一个第二蚀刻工艺以选择性地移除基本上所有的牺牲材料部分 的翅片相对于基底。

公开(公告)号：US20150270398A1

公开(公告)日：2015-09-24

申请号：US14223373

申请日：2014-03-24

Applicant: STMicroelectronics, Inc. ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Abstract translation: 所公开的一种方法包括形成由半导体材料，第一外延半导体材料和第二外延半导体材料构成的鳍状结构，在鳍状结构之上形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物 执行至少一个蚀刻工艺以去除位于侧壁间隔件外侧的翅片结构的部分，从而在该装置的源极/漏极区域中限定翅片空腔并且暴露位于该侧壁间隔之下的翅片结构的边缘 并且执行外延沉积工艺以在位于侧壁间隔件下方和翅片腔内的翅片结构的暴露边缘上形成外延蚀刻停止层。

公开(公告)号：US20150214369A1

公开(公告)日：2015-07-30

申请号：US14164934

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Bharat V. Krishnan ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Ajey Poovannummoottil Jacob ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L29/26 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/26 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract translation: 本文公开的一种说明性器件包括在具有晶体结构的半导体衬底中限定的鳍，其中鳍的至少一个侧壁基本上位于衬底的100°结晶方向，位于鳍周围的栅极结构， 侧壁间隔物，其位于栅极结构的相对侧附近，以及外延半导体材料，其围绕位于器件的源极/漏极区域中的最外侧壁间隔物横向外侧的翅片周围形成，其中外延半导体材料具有基本上均匀的厚度 沿翅片的侧壁。

公开(公告)号：US20150179644A1

公开(公告)日：2015-06-25

申请号：US14615762

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US10921526B2

公开(公告)日：2021-02-16

申请号：US16515779

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/34 ,  G02B6/12 ,  F21V8/00

Abstract: Structures for a grating coupler and methods of fabricating a structure for a grating coupler. A silicide layer is formed on a patterned section of a semiconductor layer. The grating structures of a grating coupler are formed over the silicide layer and the section of the semiconductor layer.