公开(公告)号：US09645486B2

公开(公告)日：2017-05-09

申请号：US14560388

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chin Teong Lim ,  Guoxiang Ning ,  Paul Ackmann

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36

Abstract: Methods of calibrating an OPC model using converged results of CD measurements from at least two locations along a substrate profile of a 1D, 2D, or critical area structure are provided. Embodiments include calibrating an OPC model for a structure to be formed in a substrate; simulating a CD of the structure at at least two locations along a substrate profile of the structure using the OPC model; comparing the simulated CD of the structure at each location against a corresponding measured CD; recalibrating the OPC model based on the comparing of each simulated CD against the corresponding measured CD; repeating the steps of simulating, comparing, and recalibrating until comparing at a first of the at least two locations converges to a first criteria and comparing at each other of the at least two locations converges to a corresponding criteria; and forming the structure using the recalibrated OPC model.

公开(公告)号：US09329471B1

公开(公告)日：2016-05-03

申请号：US14533497

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Xintuo Dai ,  Huang Liu ,  Chin Teong Lim

IPC: G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/20 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/34

Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

Abstract translation: 实现基于抗蚀剂特性的特征的关键尺寸目标。 建立掩模数据用于制造光刻掩模以将抗蚀剂的不同区域暴露于高，低和中等曝光水平。 抗蚀剂被配置为当暴露于高或低曝光水平时表现出高溶解度，并且当暴露于中等曝光水平时具有低溶解度。 确定抗蚀剂暴露于中间曝光水平的区域的关键尺寸，并且建立掩模数据以指示用于在光刻掩模上形成的不透明区域。 排列不透明区域以便于将抗蚀剂的区域暴露于中间曝光水平，以获得确定的临界尺寸。 此外，提供了一种用于从衬底材料上方的掩模层原位形成图案化掩模的方法。

公开(公告)号：US09323882B2

公开(公告)日：2016-04-26

申请号：US14228611

申请日：2014-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Guido Ueberreiter ,  Lloyd C. Litt ,  Paul Ackmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract translation: 提供了一种用于电路结构的度量图案布局，包括多个象限的计量图案布局，其中可以将象限第一晶片测量图案，第二晶片测量图案，标线片配准图案和掩模版测量图案布置成 有助于光栅测量数据与晶圆计量数据的相关性。 标线片配准图案还可以包括被设计成保护掩模版测量图案内的其它结构元件的一个或多个最外面的结构元件在光学邻近校正过程中被修改。 提供了一种光学邻近校正处理方法，其中可以获得分划板测量图案并将其分类以添加或修改光学邻近校正处理的规则集。

公开(公告)号：US20150028482A1

公开(公告)日：2015-01-29

申请号：US13948442

申请日：2013-07-23

Applicant: Globalfoundries Inc.

Inventor： Guoxiang Ning ,  Ming Lei ,  Paul Ackmann

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for reducing through-silicon via (TSV) stress are provided. Specifically, provided is a device comprising a substrate and a TSV formed in the substrate, the TSV having an element patterned therein. The TSV further comprises a set of openings adjacent the element that are subsequently filled with a TSV fill material. The element may be patterned according to any number of shapes (e.g., circle, oval, rectangle, etc.) to optimize the stress distribution for the TSV. The element is patterned and provided within the TSV in order to reduce or compensate for stress forces caused by a change in volume of the conductive fill materials of the openings of the TSV. These approaches apply to both single TSVs and a plurality of TSVs (e.g., arranged as a matrix).

Abstract translation: 提供了减少硅通孔（TSV）应力的方法。 具体地，提供了包括在基板中形成的基板和TSV的器件，TSV具有图案化的元件。 TSV还包括邻近该元件的一组开口，随后填充有TSV填充材料。 元件可以根据任何数量的形状（例如，圆形，椭圆形，矩形等）进行图案化，以优化TSV的应力分布。 元件被图案化并提供在TSV内，以便减少或补偿由TSV的开口的导电填充材料的体积变化引起的应力。 这些方法适用于单个TSV和多个TSV（例如，排列为矩阵）。

公开(公告)号：US10816483B2

公开(公告)日：2020-10-27

申请号：US16233336

申请日：2018-12-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jed H. Rankin ,  Guoxiang Ning ,  Paul W. Ackmann ,  Jung-Yu Hsieh ,  Ming Lei

IPC: G01N21/956 ,  G03F7/20 ,  G06T7/00

Abstract: A reticle inspection system and related method are disclosed. The system includes a concave spherical mirror positioned adjacent a side of the reticle that is configured to reflect inspection light transmitted through the reticle back towards and through the reticle. A sensor is configured to create at least one of: a first inspection image representative of a circuit pattern of the reticle based on transmission of the inspection light through the first side of the reticle and a reflection thereof by the concave spherical mirror through the second side of the reticle, and a second inspection image representative of the circuit pattern of the reticle based on the reflection of the inspection light from the first side of the reticle. A controller is configured to identify a defect in the reticle based on at least one of the first inspection image and the second inspection image.

公开(公告)号：US20200020531A1

公开(公告)日：2020-01-16

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US10324381B1

公开(公告)日：2019-06-18

申请号：US16159877

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Erfeng Ding ,  Guoxiang Ning

IPC: G01B11/00 ,  G03F7/20 ,  H01L21/768 ,  H01L27/088 ,  G06F17/50

Abstract: A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.

公开(公告)号：US20190101834A1

公开(公告)日：2019-04-04

申请号：US15720182

申请日：2017-09-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Liang Cao ,  Wenchao Jiang ,  Guoxiang Ning ,  Jie Zhang

IPC: G03F7/20 ,  G05B13/04

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/704 ,  G05B13/042 ,  G05B13/048

Abstract: Various aspects include vectorization approaches for model-based mask proximity correction (MPC). In some cases, a computer-implemented method includes: assigning a set of vectors to geometry data describing at least one mask for forming an integrated circuit (IC); adjusting a statistical predictive model of the at least one mask based upon the set of vectors and the geometry data; predicting an adjustment to the at least one mask with the statistical predictive model; and adjusting instructions for forming the at least one mask in response to a predicted mask result of the statistical predictive model deviating from a target mask result for the at least one mask.

公开(公告)号：US10199271B1

公开(公告)日：2019-02-05

申请号：US15693651

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Guillaume Bouche ,  Laertis Economikos ,  Lei Sun ,  Guoxiang Ning ,  Xunyuan Zhang

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L23/535 ,  H01L21/285 ,  H01L23/532 ,  H01L23/528

Abstract: A structure and method for forming a self-aligned metal wire on a contact structure. The method for forming the self-aligned metal wire and contact structure may include, among other things, forming an initial contact structure above a substrate; forming a patterned mask on the initial contact structure, the mask including an opening; using the patterned mask to form an opening through the initial contact structure; forming a dielectric layer in the openings; removing the patterned mask to expose a remaining portion of the initial contact structure; and forming the metal wire on the remaining portion of the initial contact structure. The contact structure may include a vertical cross-sectional geometry including one of a trapezoid wherein a bottommost surface of the first contact structure is wider than an uppermost surface of the first contact structure, and a parallelogram. The metal wire may completely contact an uppermost surface of the contact structure.

公开(公告)号：US20180337045A1

公开(公告)日：2018-11-22

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/027

CPC classification number: H01L21/0276 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76879

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.