公开(公告)号：US10535674B2

公开(公告)日：2020-01-14

申请号：US15653661

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US10224342B2

公开(公告)日：2019-03-05

申请号：US15644968

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul

IPC: H01L27/12 ,  H01L29/93 ,  H01L21/84 ,  H01L29/786 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.

公开(公告)号：US20170309643A1

公开(公告)日：2017-10-26

申请号：US15644968

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/93 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/93

Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.

公开(公告)号：US20170271484A1

公开(公告)日：2017-09-21

申请号：US15498652

申请日：2017-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L27/11521 ,  H01L21/768

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

公开(公告)号：US20160276428A1

公开(公告)日：2016-09-22

申请号：US14658361

申请日：2015-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Peter Javorka

IPC: H01L29/06 ,  H01L29/66 ,  H03K17/687 ,  H01L21/762 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L21/76283 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/76254 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/4975 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/78624 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided including a substrate, a buried oxide layer formed over the substrate, a semiconductor layer formed over the buried oxide layer, and a transistor device including a gate electrode, a gate insulation layer and a channel region, wherein the gate insulation layer comprises a part of the buried oxide layer.

Abstract translation: 提供了一种半导体器件，包括衬底，在衬底上形成的掩埋氧化物层，形成在掩埋氧化物层上的半导体层，以及包括栅电极，栅绝缘层和沟道区的晶体管器件，其中栅极绝缘 层包括一部分掩埋氧化物层。

公开(公告)号：US08962414B1

公开(公告)日：2015-02-24

申请号：US13954530

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823425 ,  H01L21/823468 ,  H01L29/6656

Abstract: In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures. After performing an implantation sequence into the sidewall spacers using adjacent gate structures as implantations masks, shadowing lower portions of the sidewall spacers, an etching process is performed for removing implanted portions from the sidewall spacers, leaving lower shadowed portions of the sidewall spacer as shaped sidewall spacers.

Abstract translation: 在本公开的方面，在制造期间的非常早的阶段提供了栅极电介质的可靠封装。 在其他方面，提供了一种半导体器件，其中保持了栅极电介质材料的可靠封装，可靠的封装存在于制造期间的早期阶段。 在实施例中，在半导体衬底的表面上设置具有多个栅极结构的半导体器件。 侧壁间隔件形成在表面上并且与多个栅极结构中的每一个相邻，其中侧壁间隔物覆盖多个栅极结构中的每一个的侧壁表面。 在使用相邻栅极结构作为注入掩模的侧壁间隔件中进行植入序列之后，遮蔽侧壁间隔物的下部，执行蚀刻工艺以从侧壁间隔物去除植入部分，从而使侧壁间隔件的较低阴影部分成为成形侧壁 间隔物

公开(公告)号：US20140335668A1

公开(公告)日：2014-11-13

申请号：US14446797

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L23/00 ,  H01L29/66

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad.

Abstract translation: 形成导电接触着陆焊盘和晶体管的方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，并执行蚀刻工艺以去除 形成在第二有源区上的栅极绝缘材料层，从而露出第二有源区。 该方法还包括执行公共处理操作，以在晶体管的第一有源区上形成栅极绝缘材料层上方的栅电极结构，以及与第二有源区导电耦合的导电接触着陆焊盘，并形成接触 到导电接触着陆垫。

公开(公告)号：US08823149B2

公开(公告)日：2014-09-02

申请号：US13710575

申请日：2012-12-11

Applicant: GlobalFoundries Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L23/495 ,  H01L21/31

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad.

Abstract translation: 本文中的一个器件包括第一和第二间隔开的有源区，形成在第一有源区中和之上的晶体管，其中晶体管具有栅电极，耦合到第二有源区的导电接触着陆焊盘，其中接触着地 焊盘由与栅极电极相同的导电材料制成，以及耦合到触点着陆焊盘的触点。 这里的一种方法包括形成第一和第二间隔开的有源区域，在有源区域上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区域上的栅极绝缘材料，执行共同的工艺操作以形成 位于第一有源区上的栅极绝缘材料上方的栅极电极结构和与第二有源区导电耦合并形成与接触着陆焊盘接触的触点接合焊盘。

公开(公告)号：US20140167119A1

公开(公告)日：2014-06-19

申请号：US13713085

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Javorka ,  Juergen Faul ,  Bastian Haussdoerfer

IPC: H01L29/78 ,  H01L21/314

CPC classification number: H01L29/7833 ,  H01L21/31116 ,  H01L21/314 ,  H01L29/66598 ,  H01L29/78

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract translation: 公开了一种形成间隔物的方法，其包括在蚀刻停止层上方形成间隔物材料层，在间隔物材料层上进行第一主蚀刻工艺以去除一些材料，在暴露蚀刻停止点之前停止蚀刻工艺 层，并且使用以下参数对间隔材料层进行第二过蚀刻工艺：约50-200scscm的惰性气体流速，约3-20scscm的反应气体流速，钝化气体流速 约3-20sccm的加工压力，约5-15mT的加工压力，用于离子产生的约200-500W的功率水平和约300-500V的偏置电压。一种器件包括位于半导体衬底上方的栅极结构 位于栅极结构附近的基本为三角形的侧壁间隔件，以及位于间隔件和栅极结构之间的蚀刻停止层。

公开(公告)号：US20140151816A1

公开(公告)日：2014-06-05

申请号：US13689979

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.

Abstract translation: 一个器件包括形成在半导体衬底中的第一和第二间隔开的有源区，位于第一有源区上的栅极绝缘材料层，和具有位于栅绝缘材料上方的第一部分的导线特征，以及第二部分 导电地接触第二活性区域。 一种方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区上的栅极绝缘材料的一部分 区域以暴露第二有源区域的一部分，以及形成导线特征，其包括位于形成在第一有源区上的栅绝缘材料层之上的第一部分和与第二有源区的暴露部分导电接触的第二部分 地区。