公开(公告)号：US20170373007A1

公开(公告)日：2017-12-28

申请号：US15698793

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Keith H. Tabakman ,  Patrick D. Carpenter ,  Guillaume Bouche ,  Michael V. Aquilino

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

公开(公告)号：US09337317B2

公开(公告)日：2016-05-10

申请号：US14697670

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/28 ,  H01L21/266 ,  H01L29/78 ,  H01L27/06 ,  H01L29/861 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/823431 ,  H01L27/0629 ,  H01L29/6609 ,  H01L29/66128 ,  H01L29/785 ,  H01L29/8611

Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.

公开(公告)号：US09318578B2

公开(公告)日：2016-04-19

申请号：US13628561

申请日：2012-09-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

Abstract translation: 通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。 由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。

公开(公告)号：US09899525B2

公开(公告)日：2018-02-20

申请号：US15592597

申请日：2017-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: This disclosure relates to a fin field effect transistor including a gate structure formed on a fin. Source and drain (S/D) regions are epitaxially grown on the fin adjacent to the gate structure. The S/D regions include a diamond-shaped cross section wherein the diamond-shaped cross section includes: internal sidewalls where the fin was recessed to a reduced height, and an external top portion of the diamond-shaped cross section of the S/D regions. A contact liner is formed over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions; and contacts are formed over the contact liner and over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions.

公开(公告)号：US09577099B2

公开(公告)日：2017-02-21

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/04 ,  H01L29/45 ,  H01L21/306

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。

公开(公告)号：US09324870B2

公开(公告)日：2016-04-26

申请号：US14020923

申请日：2013-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

Abstract translation: 通过控制半导体鳍片的表面上沉积的半导体材料的生长速率，可以在同一衬底上同时形成半导体鳍片上的合并和未熔合的凸起的有源区域。 在一个实施例中，生长速率缓冲掺杂剂可以通过成角度的离子注入注入第一半导体鳍片的侧壁表面上，在第二半导体鳍片被掩模层掩蔽的同时，其中需要延长生长速率。 在另一个实施例中，通过离子注入可以将生长速率增强掺杂剂注入到第二半导体鳍片的侧壁表面上，而第一半导体鳍片被掩蔽层掩蔽。 沉积的半导体材料的不同的生长速率可以使得第一半导体散热片上的凸起的有源区域保持不熔化，并且使第二半导体鳍片上的有源区域升高以合并。

公开(公告)号：US09105559B2

公开(公告)日：2015-08-11

申请号：US14028517

申请日：2013-09-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Nathaniel Berliner ,  Hyun-Jin Cho ,  Johnathan Faltermeier ,  Kam-Leung Lee ,  Tenko Yamashita

IPC: H01L21/00 ,  H01L21/18 ,  H01L21/225

CPC classification number: H01L21/18 ,  H01L21/2236 ,  H01L21/2251 ,  H01L21/845 ,  H01L29/66803

Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

Abstract translation: 在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。 在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。 在第二示例性实施例中，NFET鳍和PFET鳍之一可以被第一掺杂剂组合物覆盖，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，接着进行退火以在两种掺杂剂中驱动。