公开(公告)号：US09882081B2

公开(公告)日：2018-01-30

申请号：US15227081

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L27/144 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/105 ,  H01L31/18 ,  H01L31/103 ,  H01L27/146 ,  H01L31/0232

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

公开(公告)号：US09754067B2

公开(公告)日：2017-09-05

申请号：US14665242

申请日：2015-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Bertrand Gabillard ,  Phillippe Hauviller ,  Michel Rivier

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature.

公开(公告)号：US20170162743A1

公开(公告)日：2017-06-08

申请号：US15441345

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/0352 ,  H01L31/0392 ,  H01L31/0312

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09236499B2

公开(公告)日：2016-01-12

申请号：US14496285

申请日：2014-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L27/06 ,  G06F17/50 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract translation: 结场效应晶体管和结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US10833153B2

公开(公告)日：2020-11-10

申请号：US15703220

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi Liu ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/84 ,  H01L21/764 ,  H01L21/762 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.

公开(公告)号：US10580893B2

公开(公告)日：2020-03-03

申请号：US15947364

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L21/324 ,  H01L23/10 ,  H01L29/06 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

公开(公告)号：US10511143B2

公开(公告)日：2019-12-17

申请号：US15692136

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Ellis-Monaghan ,  Sebastian Ventrone ,  Vibhor Jain ,  Yves Ngu

IPC: H01S5/00 ,  H01S5/062 ,  H01S5/022 ,  H01S5/026 ,  H01S5/183 ,  H01S5/223 ,  H01S5/22

Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.

公开(公告)号：US10509244B1

公开(公告)日：2019-12-17

申请号：US16216027

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  John J. Pekarik

IPC: G02F1/01

Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.

公开(公告)号：US10461152B2

公开(公告)日：2019-10-29

申请号：US15645655

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10090330B2

公开(公告)日：2018-10-02

申请号：US15901997

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Terence B. Hook ,  Kirk D. Peterson

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/66 ,  H01L21/84 ,  H01L27/11 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.