公开(公告)号：US08889544B2

公开(公告)日：2014-11-18

申请号：US13028889

申请日：2011-02-16

申请人： Yung-Hsu Wu ,  Hsin-Hsien Lu ,  Tien-I Bao ,  Shau-Lin Shue

发明人： Yung-Hsu Wu ,  Hsin-Hsien Lu ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/311 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC分类号： H01L21/3212 ,  H01L21/02203 ,  H01L21/02348 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.

摘要翻译： 本公开提供了进行金属化学机械抛光（CMP）而不显着损失铜和镶嵌结构的介电膜的机理。 这些机制使用由具有致孔剂的低k电介质膜制成的金属CMP停止层，这显着地降低了通过金属CMP的金属CMP停止层的去除速率。 在固化（或固化）之后，将金属CMP停止层转化为多孔低k电介质膜以去除或转化致孔剂。 金属CMP停止层的低k值（例如等于或小于约2.6）使得金属CMP停止层的使用对RC延迟的影响从最小到无。 此外，CMP停止层保护下面的多孔低k电介质膜不暴露于CMP浆料中的水，有机化合物和移动离子。

公开(公告)号：US08652962B2

公开(公告)日：2014-02-18

申请号：US13526640

申请日：2012-06-19

申请人： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

发明人： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

摘要翻译： 一种形成用于半导体器件的双镶嵌金属互连的方法。 该方法包括形成低k电介质层，通过低k电介质层形成通孔，沉积牺牲层，通过牺牲层形成沟槽，用金属填充通孔和沟槽，去除牺牲层，然后沉积 极低k电介质层填充沟槽之间。 该方法允许形成用于第二级双镶嵌结构的极低k电介质层，同时通过沟槽蚀刻和沟槽金属沉积等工艺避免对该层的损伤。 该方法具有避免通孔级电介质和沟槽级电介质之间的蚀刻停止层的额外优点。

公开(公告)号：US20130334700A1

公开(公告)日：2013-12-19

申请号：US13526640

申请日：2012-06-19

申请人： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

发明人： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L23/48 ,  H01L21/283 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

摘要翻译： 一种形成用于半导体器件的双镶嵌金属互连的方法。 该方法包括形成低k电介质层，通过低k电介质层形成通孔，沉积牺牲层，通过牺牲层形成沟槽，用金属填充通孔和沟槽，去除牺牲层，然后沉积 极低k电介质层填充沟槽之间。 该方法允许形成用于第二级双镶嵌结构的极低k电介质层，同时通过沟槽蚀刻和沟槽金属沉积等工艺避免对该层的损伤。 该方法具有避免通孔级电介质和沟槽级电介质之间的蚀刻停止层的额外优点。

公开(公告)号：US20130216177A1

公开(公告)日：2013-08-22

申请号：US13399098

申请日：2012-02-17

申请人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/122 ,  B32B38/10 ,  B32B37/02

CPC分类号： G02B6/12004 ,  G02B6/0083 ,  G02B6/132 ,  G02B6/136 ,  G02B6/138 ,  G02B6/4214 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12121 ,  G02B2006/12176

摘要： A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

摘要翻译： 公开了一种制造波导器件的方法。 该方法包括提供具有选通互连区域和波导区域的衬底，并且在电互连区域中的衬底上形成图案化电介质层和图案化再分配层（RDL）。 该方法还包括通过结合堆叠将图案化的RDL结合到垂直腔表面发射激光器（VCSEL）。 在波导区域的基板上形成反射镜沟槽，反射层形成在波导区域内的反射镜区域的上方。 该方法还包括在波导区域内的波通道区域中形成和图案化底包层，并且在波导区域中形成和图案化芯层和顶包层。

公开(公告)号：US20120074535A1

公开(公告)日：2012-03-29

申请号：US12893374

申请日：2010-09-29

申请人： Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L29/06 ,  H01L21/31 ,  C09D183/06

CPC分类号： H01L21/02203 ,  C08G77/50 ,  C09D183/14 ,  C23C16/30 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.

摘要翻译： 本公开提供了包括低介电常数材料和添加剂的介电材料。 添加剂包括具有Si-X-Si桥的化合物，其中X是1至8之间的碳原子数。该添加剂可以包括末端Si-CH 3基团。 包括添加剂的电介质材料可以用作半导体器件的层间电介质（ILD）层。 可以使用CVD或溶胶 - 凝胶法形成包括添加剂的电介质材料。 添加剂的一个实例是双（三乙氧基甲硅烷基）乙烯。

公开(公告)号：US20140021611A1

公开(公告)日：2014-01-23

申请号：US13550951

申请日：2012-07-17

申请人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

发明人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

IPC分类号： H01L21/768 ,  H01L23/538

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

摘要翻译： 本公开涉及一种制造互连结构的方法，其中在半导体衬底上形成低k电介质层，然后在低k电介质层上形成铜或铜合金层。 铜或铜合金层被图案化和蚀刻以形成具有凹部的铜体，然后填充有低k电介质材料。 该方法允许形成镶嵌结构，而不会遇到由非平面特征和孔隙低K电介质损伤所呈现的各种问题。

公开(公告)号：US08405192B2

公开(公告)日：2013-03-26

申请号：US12893374

申请日：2010-09-29

申请人： Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/58

CPC分类号： H01L21/02203 ,  C08G77/50 ,  C09D183/14 ,  C23C16/30 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.

摘要翻译： 本公开提供了包括低介电常数材料和添加剂的介电材料。 添加剂包括具有Si-X-Si桥的化合物，其中X是1至8之间的碳原子数。该添加剂可以包括末端Si-CH 3基团。 包括添加剂的电介质材料可以用作半导体器件的层间电介质（ILD）层。 可以使用CVD或溶胶 - 凝胶法形成包括添加剂的电介质材料。 添加剂的一个实例是双（三乙氧基甲硅烷基）乙烯。

公开(公告)号：US09036956B2

公开(公告)日：2015-05-19

申请号：US13399098

申请日：2012-02-17

申请人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/12 ,  G02B6/138 ,  F21V8/00 ,  G02B6/42

CPC分类号： G02B6/12004 ,  G02B6/0083 ,  G02B6/132 ,  G02B6/136 ,  G02B6/138 ,  G02B6/4214 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12121 ,  G02B2006/12176

摘要： A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

摘要翻译： 公开了一种制造波导器件的方法。 该方法包括提供具有选通互连区域和波导区域的衬底，并且在电互连区域中的衬底上形成图案化电介质层和图案化再分配层（RDL）。 该方法还包括通过结合堆叠将图案化的RDL结合到垂直腔表面发射激光器（VCSEL）。 在波导区域的基板上形成反射镜沟槽，反射层形成在波导区域内的反射镜区域的上方。 该方法还包括在波导区域内的波通道区域中形成和图案化底包层，并且在波导区域中形成和图案化芯层和顶包层。

公开(公告)号：US08735278B2

公开(公告)日：2014-05-27

申请号：US13550951

申请日：2012-07-17

申请人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

发明人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

摘要翻译： 本公开涉及一种制造互连结构的方法，其中在半导体衬底上形成低k电介质层，然后在低k电介质层上形成铜或铜合金层。 铜或铜合金层被图案化和蚀刻以形成具有凹部的铜体，然后填充有低k电介质材料。 该方法允许形成镶嵌结构，而不会遇到由非平面特征和孔隙低K电介质损伤所呈现的各种问题。

公开(公告)号：US10180547B2

公开(公告)日：2019-01-15

申请号：US13403566

申请日：2012-02-23

申请人： Wan-Yu Lee ,  Chun-Hao Tseng ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Wan-Yu Lee ,  Chun-Hao Tseng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/42 ,  H01S5/022 ,  H01S5/00

摘要： An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.