公开(公告)号：US06610560B2

公开(公告)日：2003-08-26

申请号：US09854303

申请日：2001-05-11

申请人： Han-Ping Pu ,  Yu-Po Wang ,  Caesar Lin

发明人： Han-Ping Pu ,  Yu-Po Wang ,  Caesar Lin

IPC分类号： H01L2144

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L21/565 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A semiconductor packaging technology is proposed for the fabrication of a chip-on-chip (COC) based multi-chip module (MCM) with molded underfill. The proposed semiconductor packaging technology is characterized by the provision of a side gap of an empirically-predetermined width between the overlying chips mounted through COC technology over an underlying chip to serve as an air vent during molding process. This allows the injected molding material to flow freely into the flip-chip undergaps during molding process. In actual application, the exact width of the side gap is empirically predetermined through molded-underfill simulation experiments to find the optimal value. Based on experimental data, it is found that this side gap width should be equal to or less than 0.3 mm to allow optimal underfill effect. The optimal value for this side gap width may be varied for different package specifications.

公开(公告)号：US20080164604A1

公开(公告)日：2008-07-10

申请号：US12008202

申请日：2008-01-08

申请人： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34

CPC分类号： H01L23/3675 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2224/0401

摘要： A heat dissipating semiconductor package is disclosed, including a chip carrier; at least a semiconductor chip mounted and electrically connected to the chip carrier; and a heat dissipating member mounted on the semiconductor chip with a thermal interface material (TIM) interposed therebetween, wherein the TIM is provided with a plurality of fillers for supporting the TIM at an appropriate height, thereby preventing the TIM from being wetted so as to avoid collapsing and overflow of the TIM as a result of wetting problem.

摘要翻译： 公开了一种散热半导体封装，包括芯片载体; 至少安装并电连接到所述芯片载体的半导体芯片; 以及安装在半导体芯片上的散热构件，其间插入有热界面材料（TIM），其中所述TIM具有多个用于将TIM支撑在适当高度的填充物，从而防止TIM被润湿，从而 避免由于润湿问题导致TIM的崩溃和溢出。

公开(公告)号：US08207620B2

公开(公告)日：2012-06-26

申请号：US11880467

申请日：2007-07-20

申请人： Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/29

CPC分类号： H01L21/563 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

摘要翻译： 本发明公开了一种倒装芯片半导体封装及其芯片载体。 芯片载体包括围绕芯片安装区域形成的凹槽。 槽可以沿着芯片安装区域的周边或其拐角处形成。 凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

公开(公告)号：US07732913B2

公开(公告)日：2010-06-08

申请号：US11701767

申请日：2007-02-02

申请人： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

发明人： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

IPC分类号： H01L23/04

CPC分类号： H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

摘要翻译： 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

公开(公告)号：US07564140B2

公开(公告)日：2009-07-21

申请号：US11411740

申请日：2006-04-25

申请人： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

摘要翻译： 提供半导体封装及其基板结构。 施加在基板结构上的焊接掩模层形成有对应于基板结构的芯片安装区域的角部的向外延伸的开口。 当倒装芯片半导体芯片安装在芯片安装区域并执行底部填充工艺时，底部填充材料可以填充倒装芯片半导体芯片和基板结构之间的间隙，并且有效地填充焊料的向外延伸的开口 掩模层对应于芯片安装区域的角部，以便为倒装芯片半导体芯片的拐角提供足够的保护，并防止在随后的热循环期间倒装芯片半导体芯片的拐角处的分层。

公开(公告)号：US20070096336A1

公开(公告)日：2007-05-03

申请号：US11411740

申请日：2006-04-25

申请人： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

摘要翻译： 提供半导体封装及其基板结构。 施加在基板结构上的焊接掩模层形成有对应于基板结构的芯片安装区域的角部的向外延伸的开口。 当倒装芯片半导体芯片安装在芯片安装区域并执行底部填充工艺时，底部填充材料可以填充倒装芯片半导体芯片和基板结构之间的间隙，并且有效地填充焊料的向外延伸的开口 掩模层对应于芯片安装区域的角部，以便为倒装芯片半导体芯片的拐角提供足够的保护，并防止在随后的热循环期间倒装芯片半导体芯片的拐角处的分层。

公开(公告)号：US20080017983A1

公开(公告)日：2008-01-24

申请号：US11880467

申请日：2007-07-20

申请人： Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

摘要翻译： 本发明公开了一种倒装芯片半导体封装及其芯片载体。 芯片载体包括围绕芯片安装区域形成的凹槽。 槽可以沿着芯片安装区域的周边或其拐角处形成。 凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

公开(公告)号：US20070273026A1

公开(公告)日：2007-11-29

申请号：US11701767

申请日：2007-02-02

申请人： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

发明人： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

IPC分类号： H01L23/488

CPC分类号： H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

摘要翻译： 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

公开(公告)号：US20080277786A1

公开(公告)日：2008-11-13

申请号：US12156874

申请日：2008-06-05

申请人： Chun-Lung Chen ,  Yu-Po Wang ,  Jeng-Yuan Lai ,  Cheng-Hsu Hsiao

发明人： Chun-Lung Chen ,  Yu-Po Wang ,  Jeng-Yuan Lai ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48

CPC分类号： H05K1/115 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/112 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10674 ,  H01L2224/0401

摘要： A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate.

摘要翻译： 半导体封装基板包括具有彼此相对的上表面和下表面的主体，形成在主体中的多个电路层，形成在主体的上表面上的多个焊盘，以及多个焊球 衬垫形成在身体的下表面上。 每个焊盘通过设置在电路层之间的电路层和导电结构电连接到焊球之一，其中电路层和导电结构被配置为以扇出方式向外扩展，以便提供 电路层之间的距离更靠近主体的下表面的空间更多，使得焊料焊盘 - 焊球焊盘电连接的一部分可以包括形成在该空间中的多个平行连接的导电结构，从而增强导热通道和效果 的散热而不必在基板的表面上设置更多的焊盘。

公开(公告)号：US20080150128A1

公开(公告)日：2008-06-26

申请号：US12004779

申请日：2007-12-21

申请人： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34 ,  H01L21/02

CPC分类号： H01L23/42 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/838 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3512

摘要： A heat dissipating chip structure and a fabrication method thereof and a package having the same are provided. The fabrication method mainly includes: forming a metal layer on an non-active surface of a wafer having a plurality of chips with the metal layer thereof providing a better solder bonding with a thermal interface material at positions corresponding to centers of each chips, and not being disposed on the cutting paths between the chips to prevent crack and peel off during the cutting. Further, when the chips are subsequently mounted on a chip carrier and further attached to a heat dissipating sheet with another metal layer on a surface thereof with the thermal interface material (TIM), with different surface areas of the metal layers formed on the heat dissipating sheet and the chip, an inward and downward force is generated in the TIM to limit an wetting area.

摘要翻译： 散热芯片结构及其制造方法以及具有该散热芯片的封装。 该制造方法主要包括：在具有多个芯片的晶片的非活性表面上形成金属层，其金属层与对应于每个芯片的中心的位置处的热界面材料提供更好的焊接，而不是 设置在切屑之间的切割路径上，以防止切割期间的裂纹和剥离。 此外，当芯片随后安装在芯片载体上并且进一步连接到具有热界面材料（TIM）的表面上的另一金属层的散热片时，在散热片上形成的金属层的不同表面积 片材和芯片，TIM中产生向内和向下的力以限制润湿区域。