公开(公告)号：US5095358A

公开(公告)日：1992-03-10

申请号：US510742

申请日：1990-04-18

申请人： Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

发明人： Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

IPC分类号： H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L29/161

CPC分类号： H01L29/161 ,  H01L21/22 ,  H01L21/26506

摘要： A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

公开(公告)号：US20050179138A1

公开(公告)日：2005-08-18

申请号：US11104763

申请日：2005-04-12

申请人： Vladimir Zubkov ,  Sheldon Aronowitz

发明人： Vladimir Zubkov ,  Sheldon Aronowitz

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L21/76831 ,  H01L21/76802

摘要： A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

摘要翻译： 提供了一种用于半导体器件的阻挡层。 该半导体器件包括电介质层，导电含铜层和将电介质层与含铜层隔开的阻挡层。 阻挡层包括氧化硅层和掺杂剂，其中掺杂剂是二价离子，其掺杂与含铜层相邻的氧化硅层。 提供形成阻挡层的方法。 提供具有表面的氧化硅层。 氧化硅层的表面掺杂有二价离子以形成延伸到氧化硅层的表面的势垒层。 在阻挡层的表面上形成导电含铜层，其中阻挡层防止铜扩散到衬底中。

公开(公告)号：US06897102B2

公开(公告)日：2005-05-24

申请号：US10313333

申请日：2002-12-06

申请人： Sheldon Aronowitz ,  Mohammed Mirabedini

发明人： Sheldon Aronowitz ,  Mohammed Mirabedini

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/51 ,  H01L31/113

CPC分类号： H01L21/28194 ,  H01L21/28176 ,  H01L29/513 ,  H01L29/517

摘要： A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate dielectric. Polysilicon is deposited onto the calcium and patterned in a standard way. The exposed calcium is then removed by raising the temperature to approximately 600° C. The calcium remaining between the gate dielectric and the polysilicon blocks channeling of dopant to minimize depletion and penetration, increase conductivity, and allow for longer and higher-temperature annealing.

摘要翻译： 揭示了制备多晶硅栅极以最小化栅极耗尽和掺杂剂穿透并增加电导率的方法。 几个原子的单层会凝结在栅极电介质上。 多晶硅沉积在钙上并以标准方式图案化。 然后通过将温度升高至约600℃来除去暴露的钙。残留在栅极电介质和多晶硅之间的钙阻挡掺杂剂的通道，以使耗尽和穿透最小化，增加导电性，并允许更长时间和更高温退火。

公开(公告)号：US20050098856A1

公开(公告)日：2005-05-12

申请号：US10652007

申请日：2003-08-29

申请人： Sheldon Aronowitz ,  Vladimir Zubkov

发明人： Sheldon Aronowitz ,  Vladimir Zubkov

IPC分类号： C01B33/12 ,  C23C16/40 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31 ,  H01L23/58

CPC分类号： H01L21/02126 ,  C01B33/126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  Y02P20/129

摘要： The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C—C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

公开(公告)号：US06572925B2

公开(公告)日：2003-06-03

申请号：US09792683

申请日：2001-02-23

申请人： Vladimir Zubkov ,  Sheldon Aronowitz

发明人： Vladimir Zubkov ,  Sheldon Aronowitz

IPC分类号： C23C1640

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31629

摘要： A process is provided for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes including one or more organofluoro silanes characterized by the absence of aliphatic C—H bonds. In one embodiment, the process is carried out using a mild oxidizing agent. Also provided is a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material for use in an integrated circuit structure containing silicon atoms bonded to oxygen atoms, silicon atoms bonded to carbon atoms, and carbon atoms bonded to fluorine atoms, where the dielectric material is characterized by the absence of aliphatic C—H bonds and where the dielectric material has a ratio of carbon atoms to silicon atoms of C:Si greater than about 1:3.

摘要翻译： 提供一种通过与氧化剂反应形成低k含氟和碳的氧化硅介电材料的方法，所述氧化剂包括一种或多种包含一种或多种以不存在脂族C-H键的有机氟硅烷的硅烷。 在一个实施方案中，该方法使用温和的氧化剂进行。 还提供了一种用于集成电路结构的低介电常数含氟和含碳氧化硅电介质材料，该集成电路结构包含与氧原子键合的硅原子，与碳原子键合的硅原子和与氟原子键合的碳原子，其中电介质材料 其特征在于不存在脂族CH键，并且其中介电材料具有大于约1:3的C：Si的碳原子与硅原子的比例。

公开(公告)号：US06246093B1

公开(公告)日：2001-06-12

申请号：US08719773

申请日：1996-09-25

申请人： Lindor E. Henrickson ,  Sheldon Aronowitz

发明人： Lindor E. Henrickson ,  Sheldon Aronowitz

IPC分类号： H01L2978

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/7835 ,  H01L29/7838

摘要： A MOSFET having a buried channel structure and an adjacent surface channel structure between a source region and a drain region. The surface channel structure is preferably formed adjacent the source region via angular implantation techniques. By combining the advantages of the surface channel device with the buried channel device, the resulting hybrid MOSFET structure has improved drive current and switching characteristics.

摘要翻译： 具有掩埋沟道结构的MOSFET和源极区域和漏极区域之间的相邻表面沟道结构。 表面通道结构优选通过角度注入技术形成在源区附近。 通过结合表面沟道器件与掩埋沟道器件的优点，所得到的混合MOSFET结构具有改进的驱动电流和开关特性。

公开(公告)号：US6093936A

公开(公告)日：2000-07-25

申请号：US918577

申请日：1997-08-19

申请人： Abraham Yee ,  Sheldon Aronowitz ,  Yu-Lam Ho

发明人： Abraham Yee ,  Sheldon Aronowitz ,  Yu-Lam Ho

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L27/06 ,  H01L29/04

CPC分类号： H01L27/0688 ,  H01L21/26506 ,  H01L21/76213

摘要： A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles. Also, the amorphous silicon relieves surface layer stresses which may be present from prior processes or because of prior morphological structural elements formed on the silicon substrate. A boron ion bombardment may also be used to further inhibit loss of P-well dopant to the oxidant forming the field oxidation layer and preserving a desired high field threshold voltage and robust field isolation for the integrated circuit.

摘要翻译： 硅半导体集成电路包括基本上不会侵入集成电路的有源电路元件的绝缘场氧化层。 场氧化层由通过用惰性气体离子轰击硅衬底产生的氧化非晶硅形成。 非晶硅以比结晶硅更快的速度氧化，使得当形成场氧化层时，用于有源电路元件的晶体硅基底基本保持不变。 在惰性气体离子轰击期间，通过使用适当的屏蔽元件形成晶体硅基底。 这种惰性气体离子轰击还具有消除场氧化区域中可能存在的位错缺陷的优点，使得这些缺陷在随后的加热和冷却循环期间不会传播到硅的晶格中。 此外，非晶硅减轻了可能存在于现有工艺中的表面层应力或由于在硅衬底上形成的先前形态结构元件。 还可以使用硼离子轰击来进一步抑制形成场氧化层的氧化剂的P阱掺杂剂的损失，并且为集成电路保留期望的高场阈值电压和鲁棒的场隔离。

公开(公告)号：US6033998A

公开(公告)日：2000-03-07

申请号：US38684

申请日：1998-03-09

申请人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

发明人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

IPC分类号： H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823462

摘要： Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.

摘要翻译： 提供一种制造在半导体晶片的不同区域上具有可变厚度和组成的栅极电介质层的方法。 在本发明的优选实施例中，首先在各个区域上生长栅氧化层。 具有相对较厚，未硬化的栅极电介质的区域被掩蔽，并且晶片暴露于远程低能量氮等离子体。 在氮化处理完成之后，去除掩模并使晶片进一步氧化。 已经形成氮氧化物的区域用作氧化过程的屏障。 因此，可以在相同的晶片上生长不同的氧化物厚度，在已经进行氮化的情况下更薄并且硬化，并且在氮化期间被掩蔽的那些区域中较厚而不硬化。 根据本发明的可变厚栅极电介质在涉及数字和模拟装置的半导体集成电路中可能是特别有利的。

公开(公告)号：US5904551A

公开(公告)日：1999-05-18

申请号：US631360

申请日：1996-04-12

申请人： Sheldon Aronowitz ,  James Kimball

发明人： Sheldon Aronowitz ,  James Kimball

IPC分类号： H01L21/265 ,  H01L21/70

CPC分类号： H01L21/26513 ,  H01L21/26586

摘要： A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

摘要翻译： 公开了一种用于通过以低能量注入（包括使半导体衬底的晶格定向）来在单晶半导体衬底的表面下方形成一个或多个掺杂区域（例如逆行阱或较深源极/漏极区域）的方法， 到注入光束的轴线，即注入光束中的激发原子的路径，以使在晶格中的原子之间通过的注入原子的数量最大化。 这导致单晶半导体衬底的晶格中的注入原子的峰值浓度比衬底中注入原子的峰值浓度更深，如果注入光束的轴不相对于晶格取向 的半导体衬底。

公开(公告)号：US5707888A

公开(公告)日：1998-01-13

申请号：US434674

申请日：1995-05-04

申请人： Sheldon Aronowitz ,  James Kimball

发明人： Sheldon Aronowitz ,  James Kimball

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S438/911

摘要： A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer. The initial oxide formed by the process appears to be temperature independent, at temperatures of 900.degree. C. or less, with oxide formation apparently dependent upon the extent of the implanted regions of the substrate, rather than upon temperature, resulting in thermal savings. Furthermore, the excess implanted noble gas in the substrate adjacent the oxide formed therein can have beneficial effects in inhibiting the formation of parasitic field transistors and in greater control over field thresholds.