公开(公告)号：US06673714B2

公开(公告)日：2004-01-06

申请号：US10133605

申请日：2002-04-25

Applicant: Heon Lee ,  Thomas C. Anthony ,  Lung T. Tran

Inventor： Heon Lee ,  Thomas C. Anthony ,  Lung T. Tran

IPC: H01L214763

CPC classification number: H01L21/0338 ,  H01L21/0273 ,  H01L21/0337 ,  Y10S438/947

Abstract: A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched. The second polymer layer is made from a photo active material and is operative as an etch mask for the first photoresist layer. The etching is continued until the first polymer layer has a sub-lithographic feature size that is less than a lithography limit of a lithography system. A dielectric material is deposited on the etch mask and the first polymer layer. The first polymer layer is lifted-off to define a sub-lithographic sized via.

Abstract translation: 公开了一种制造亚光刻尺寸的通孔的方法。 使用双聚合物方法形成聚合物材料的堆叠层，其中第一聚合物层具有第一蚀刻速率，第二聚合物层具有第二蚀刻速率。 当第一和第二聚合物层被各向同性蚀刻时，预先选择第一蚀刻速率快于第二蚀刻速率。 第二聚合物层由光活性材料制成，并且可用作第一光致抗蚀剂层的蚀刻掩模。 继续蚀刻直到第一聚合物层具有小于光刻系统的光刻极限的亚光刻特征尺寸。 介电材料沉积在蚀刻掩模和第一聚合物层上。 第一聚合物层被剥离以确定亚光刻尺寸的通孔。

公开(公告)号：US06326260B1

公开(公告)日：2001-12-04

申请号：US09599703

申请日：2000-06-22

Applicant: Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

Inventor： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

IPC: H01L218242

CPC classification number: H01L27/10894 ,  H01L21/823462 ,  H01L27/10873

Abstract: A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.

Abstract translation: 提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。 具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层 形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层 所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及 所述多晶硅层在所述导体材料层上形成氮化物覆盖层 形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

公开(公告)号：US06284666B1

公开(公告)日：2001-09-04

申请号：US09583963

申请日：2000-05-31

Applicant: Munir D. Naeem ,  Gangadhara S. Mathad ,  Byeong Yeol Kim ,  Stephan P. Kudelka ,  Brian S. Lee ,  Heon Lee ,  Elizabeth Morales ,  Young-Jin Park ,  Rajiv M. Ranade

Inventor： Munir D. Naeem ,  Gangadhara S. Mathad ,  Byeong Yeol Kim ,  Stephan P. Kudelka ,  Brian S. Lee ,  Heon Lee ,  Elizabeth Morales ,  Young-Jin Park ,  Rajiv M. Ranade

IPC: H01L21302

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， <30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度。

公开(公告)号：US07709882B2

公开(公告)日：2010-05-04

申请号：US11255458

申请日：2005-10-20

Applicant: Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Louis Szepesi, Jr. ,  Heon Lee

Inventor： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Louis Szepesi, Jr. ,  Heon Lee

IPC: H01L29/788

CPC classification number: B82Y10/00 ,  G11B9/08 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1436 ,  G11B11/08

Abstract: A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.

Abstract translation: 存储装置包括具有p-掺杂剂的第一半导体层和具有n-掺杂剂的第二半导体层，其设置在第一半导体层上，形成第一和第二半导体层之间的结。 存储装置还包括设置在第二半导体层上的电荷捕获结构和导电栅极，其中导电栅极和电荷捕获结构相对于另一个迁移，其中施加在第二半导体层和导电栅极阱上的电场 电荷捕获结构中的电荷。

公开(公告)号：US06989327B2

公开(公告)日：2006-01-24

申请号：US10770083

申请日：2004-01-31

Applicant: Manish Sharma ,  Thomas C. Anthony ,  Heon Lee

Inventor： Manish Sharma ,  Thomas C. Anthony ,  Heon Lee

IPC: H01L21/44

CPC classification number: H01L21/0331 ,  H01L21/0272 ,  H01L21/31144 ,  H01L43/12 ,  Y10S438/951

Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.

Abstract translation: 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板，将至少一种材料沉积通过剥离模板，去除剥离模板的一部分，与剥离模板的剩余部分形成重新进入的模型并且沉积导体材料与所述脱模模板接触。 至少一个材料在入口轮廓。

公开(公告)号：US20050181293A1

公开(公告)日：2005-08-18

申请号：US10834371

申请日：2004-04-28

Applicant: Heon Lee

Inventor： Heon Lee

IPC: H01L21/027 ,  G03C5/00 ,  G03F7/00 ,  G03G13/06 ,  G03G13/20

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  G03F7/0002

Abstract: The present invention relates to an imprinting device for imprinting a pattern, and more particularly, to an imprinting device for imprinting a pattern to a size of nanometer or micrometer dimension. The imprinting device of the present invention is comprised of: a part for forming a hollow portion for accommodating a stamp formed with a pattern and transparent with respect to ultraviolet rays or infrared rays, and a base substrate formed with a polymer hardened by the ultraviolet rays or the infrared rays; an elastic plate made of an elastic material and forming a part of an inner wall of the hollow portion, the elastic plate which is so deformed by a pressure difference between inside and outside of the hollow portion that the stamp is pressed onto the polymer onto the base substrate in order that the pattern formed on a surface of the stamp is transcribed on the polymer; a transparent plate made of a material transparent with respect to the ultraviolet rays or the infrared rays and forming a part of another inner wall facing the elastic plate at the hollow portion, the transparent plate which transmits the ultraviolet rays or the infrared rays to the polymer formed with the pattern so that the polymer is hardened; and a part for discharging air in the hollow portion to be a low pressure state.

Abstract translation: 本发明涉及一种用于压印图案的压印装置，更具体地说，涉及一种用于将图案压印成尺寸为纳米或微米尺寸的压印装置。 本发明的压印装置包括：用于形成中空部分的部分，用于容纳形成有图案并且相对于紫外线或红外线透明的印模，以及形成有由紫外线硬化的聚合物的基底 或红外线; 由弹性材料制成并形成中空部分的内壁的一部分的弹性板，弹性板通过中空部分的内部和外部之间的压力差而变形，使得压印在聚合物上的弹性板 以使形成在印模表面上的图案转录在聚合物上; 由相对于紫外线或红外线透明的材料制成的透明板，并且在中空部分形成面对弹性板的另一内壁的一部分，透射板将紫外线或红外线透射到聚合物 形成图案，使得聚合物硬化; 以及将中空部中的空气排出到低压状态的部分。

公开(公告)号：US06927092B2

公开(公告)日：2005-08-09

申请号：US10656758

申请日：2003-09-05

Applicant: Heon Lee ,  Fred Perner

Inventor： Heon Lee ,  Fred Perner

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L21/00

CPC classification number: G11C11/16 ,  G11C11/15

Abstract: A method of forming a shared global word line MRAM structure is disclosed. The method includes, etching a trench in an oxide layer formed over a substrate, depositing an first liner material, anisotropically etching the deposited first liner material leaving the first liner material on edges of the trench and physically contacting a bottom of the trench, depositing an magnetic metal liner material, anisotropically etching the deposited magnetic metal liner material leaving the magnetic metal liner material over the first liner material on edges of the trench, so that the magnetic metal liner extends to and physically contacts the bottom of the trench, depositing a conductive layer;, and chemically, mechanically polishing the conductive layer.

Abstract translation: 公开了一种形成共享全局字线MRAM结构的方法。 该方法包括：蚀刻在衬底上形成的氧化物层中的沟槽，沉积第一衬里材料，各向异性地蚀刻沉积的第一衬垫材料，使第一衬垫材料留在沟槽的边缘上并物理接触沟槽的底部， 磁性金属衬垫材料，各向异性地蚀刻离开磁性金属衬垫材料的沉积的磁性金属衬垫材料在沟槽边缘上的第一衬里材料上，使得磁性金属衬垫延伸到并物理接触沟槽的底部，沉积导电 层;并且化学地，机械地抛光导电层。

公开(公告)号：US20050161431A1

公开(公告)日：2005-07-28

申请号：US10766646

申请日：2004-01-27

Applicant: Heon Lee

Inventor： Heon Lee

IPC: C03C25/68

CPC classification number: C04B35/565 ,  B81C99/009 ,  B82Y10/00 ,  B82Y40/00 ,  C04B2235/602 ,  C04B2235/94 ,  G03F7/0002

Abstract: A method of fabricating a silicon carbide imprint stamp is disclosed. A mold layer has a cavity formed therein. A spacer is formed in the cavity to reduce a first feature size of the cavity. A casting process is used to form a feature and a foundation layer connected with the feature. The spacer operatively reduces the first feature size of the feature to a second feature size that is less than the lithography limit. The foundation layer and the feature are unitary whole made from a material comprising silicon carbide (SiC), a material that is harder than silicon (Si) alone. Consequently, the silicon carbide imprint stamp has a longer service lifetime because it can endure several imprinting cycles without wearing out or breaking. The longer service lifetime makes the silicon carbide imprint stamp economically feasible to manufacture as the manufacturing cost can be recouped over the service lifetime.

Abstract translation: 公开了一种制造碳化硅印记印模的方法。 模具层中形成有空腔。 间隔件形成在空腔中以减小空腔的第一特征尺寸。 使用铸造工艺来形成与特征相连的特征和基础层。 间隔件可以将特征的第一特征尺寸减小到小于光刻极限的第二特征尺寸。 基础层和特征是由包括碳化硅（SiC）的材料制成的整体，其是单独比硅（Si）更硬的材料。 因此，碳化硅印记印模具有更长的使用寿命，因为它可以承受几个压印周期而不会磨损或断裂。 更长的使用寿命使得碳化硅印记印模经济上可行，因为制造成本可以在使用寿命内回收。

公开(公告)号：US20050136648A1

公开(公告)日：2005-06-23

申请号：US10745723

申请日：2003-12-23

Applicant: Mariah Sharma ,  Thomas Anthony ,  Heon Lee

Inventor： Mariah Sharma ,  Thomas Anthony ,  Heon Lee

IPC: H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L43/12

CPC classification number: H01L43/12

Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, depositing a dielectric material, planarizing the dielectric material thereby exposing a portion of the at least one material and depositing a conductor material in contact with the exposed portion of the at least one material.

Abstract translation: 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板，将至少一种材料沉积通过剥离模板，去除剥离模板的一部分，沉积电介质材料，平坦化介电材料，从而暴露至少一种材料的一部分并沉积导体材料 与所述至少一种材料的暴露部分接触。

公开(公告)号：US20050111341A1

公开(公告)日：2005-05-26

申请号：US10721574

申请日：2003-11-25

Applicant: Sean Zhang ,  Heon Lee

Inventor： Sean Zhang ,  Heon Lee

IPC: G11B9/14 ,  G11B7/00 ,  G11B7/0033 ,  G11B7/0045 ,  G11B7/24 ,  G11B11/00 ,  G11B11/08 ,  G11C11/35 ,  G11C11/42

CPC classification number: G11B11/00 ,  G11B7/0033 ,  G11B7/00455 ,  G11B7/24

Abstract: Method for employing optical state-change organic polymer films as information-storage layers in optoelectronic, high-density memories, and high-density optoelectronic memories produced by the method. In certain embodiments, the optical state-change organic polymer films can be manufactured to exhibit two different, stable optical states, one transparent, and one light-absorbing and/or light-reflecting, that can be locally, stably, and reversibly induced by application of an electrical field. In various embodiments, information is digitally encoded in an information-storage layer as bits, the value of each bit represented by the optical state of an area of the information-storage layer corresponding to the bit. In various embodiments, the optical state of a small region of the information-storage layer can be determined by exposing the small region to visible light, and determining whether or not a photodiode layer in an information-storage medium below the information-storage layer generates an electrical current in response to illumination.

Abstract translation: 在光电子，高密度存储器中使用光学状态变换有机聚合物膜作为信息存储层的方法，以及通过该方法制造的高密度光电存储器。 在某些实施方案中，可以制造光学状态变化的有机聚合物膜以呈现两种不同的，稳定的光学状态，一种透明的，一种光吸收和/或光反射，其可以局部，稳定和可逆地由 应用电场。 在各种实施例中，信息在信息存储层中被数字地编码为比特，每个比特的值由对应于该比特的信息存储层的区域的光学状态表示。 在各种实施例中，信息存储层的小区域的光学状态可以通过将小区域暴露于可见光来确定，并且确定在信息存储层下方的信息存储介质中的光电二极管层是否产生 响应照明的电流。