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126 条记录 (耗时 0.033 秒)

    Semiconductor memory device with redundancy circuit
    23.
    发明授权
    Semiconductor memory device with redundancy circuit 失效
    具有冗余电路的半导体存储器件

    公开(公告)号：US4858192A

    公开(公告)日：1989-08-15

    申请号：US225510

    申请日：1988-07-28

    申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/781

    摘要： A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

    摘要翻译： 半导体存储器件具有用于在发生在主存储器单元中时补偿有缺陷的位的冗余电路。 冗余电路包括备用存储单元，用于选择备用存储单元的备用排解码器​​，当使用备用行解码器时禁止使用主行解码器的第一电路部分和用于选择备用行的第二电路部分 解码器，当指定连接到有缺陷的存储单元的主行线的地址被表示时。

    Non-volatile semiconductor memory system
    24.
    发明授权
    Non-volatile semiconductor memory system 失效
    非易失性半导体存储器系统

    公开(公告)号：US4597062A

    公开(公告)日：1986-06-24

    申请号：US630863

    申请日：1984-07-16

    申请人： Masamichi Asano ,  Hiroshi Iwahashi

    发明人： Masamichi Asano ,  Hiroshi Iwahashi

    IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C29/34 ,  G11C7/00

    CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C29/34

    摘要： A non-volatile semiconductor memory system includes a memory cell array having floating gate type MOS transistors, and a boosting circuit for boosting a write voltage applied to the memory system. A distributing circuit is further contained for selectively distributing a boosted voltage from the boosting circuit to at least a part of the memory system, for example, row lines in response to a control signal.

    摘要翻译： 非易失性半导体存储器系统包括具有浮置栅型MOS晶体管的存储单元阵列和用于升压施加到存储器系统的写入电压的升压电路。 还包括分配电路，用于响应于控制信号选择性地将升压电压从升压电路分配到存储器系统的至少一部分，例如行线。

    Semiconductor integrated circuit
    27.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5214609A

    公开(公告)日：1993-05-25

    申请号：US751768

    申请日：1991-08-29

    申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Nobuaki Hiraga

    发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Nobuaki Hiraga

    IPC分类号： G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/18 ,  G11C11/407 ,  G11C11/409 ,  G11C16/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C8/18

    摘要： In the semiconductor integrated circuit, the data delay circuit and data latch circuit are connected between the sense amplifier circuit and the output buffer circuit. A pulse signal for controlling the output buffer is first generated according to a pulse output signal of the address change detection circuit, and then a latch signal which permits output data of the data detection circuit obtained before the change of the address input signal to be latched by the data latch circuit for a preset period of time is generated. Next, a delay signal is generated which sets the delay time of the data delay circuit to be short in a case where data detected by the data detection circuit is not output from the output buffer circuit, and sets the delay time of the data delay circuit to be long in a case where data is output from the output buffer circuit. Generation of the delay signal is interrupted after the pulse signal of the address change detection circuit is interrupted. As a result, the power source variation at the time of output data change or erroneous operation due to noise input from the exterior can be prevented. Further, the driving ability of the output buffer transistor can be set to a large value so that a highly reliable semiconductor integrated circuit in which the operation margin of the integrated circuit with respect to the power source variation and noise can be made large while keeping the data readout speed high can be obtained.