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129 条记录 (耗时 0.036 秒)

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    21.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
    半导体器件采用互补时钟和信号输入状态检测电路相同

    公开(公告)号：US6104225A

    公开(公告)日：2000-08-15

    申请号：US76810

    申请日：1998-05-13

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： G11C7/22 ,  H03K5/00 ,  H03K5/135 ,  H03K5/151 ,  H03L7/081 ,  G06F1/04

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    摘要翻译： 公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。 第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。 第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。 第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。 当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟 ，根据第二外部时钟状态检测电路的判断。

    Memory subsystem operated in synchronism with a clock
    22.
    发明授权
    Memory subsystem operated in synchronism with a clock 失效
    内存子系统与时钟同步运行

    公开(公告)号：US06397312B1

    公开(公告)日：2002-05-28

    申请号：US08970086

    申请日：1997-11-13

    申请人： Masao Nakano ,  Hiroyoshi Tomita ,  Kotoku Sato ,  Yoshihiro Takemae ,  Masao Taguchi

    发明人： Masao Nakano ,  Hiroyoshi Tomita ,  Kotoku Sato ,  Yoshihiro Takemae ,  Masao Taguchi

    IPC分类号： G06F1200

    CPC分类号： G06F13/4243

    摘要： A memory system having a simple configuration capable of high-speed data transmission is disclosed. Data is output from a controller or a memory in synchronism with a clock or a data strobe signal. The clock or the data strobe signal is transmitted by a clock signal line or a data strobe signal line, respectively, arranged in parallel to a data signal line. A delay circuit delays by a predetermined time the signals transmitted through the clock signal line or the data strobe signal line. The clock or the data strobe signal thus assumes a phase suitable for retrieval at the destination, so that the data signal can be retrieved directly by means of the received clock or the received data strobe signal.

    摘要翻译： 公开了一种具有能够进行高速数据传输的简单配置的存储器系统。 与时钟或数据选通信号同步地从控制器或存储器输出数据。 时钟或数据选通信号分别通过与数据信号线并联布置的时钟信号线或数据选通信号线来发送。 延迟电路在预定时间内延迟通过时钟信号线或数据选通信号线发送的信号。 因此，时钟或数据选通信号采取适合在目的地检索的相位，使得可以通过接收的时钟或接收的数据选通信号直接检索数据信号。

    RESISTANCE CHANGING MEMORY CELL ARCHITECTURE
    24.
    发明申请
    RESISTANCE CHANGING MEMORY CELL ARCHITECTURE 有权
    电阻变化存储器单元架构

    公开(公告)号：US20120051115A1

    公开(公告)日：2012-03-01

    申请号：US13289553

    申请日：2011-11-04

    申请人： Masao Taguchi

    发明人： Masao Taguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/78 ,  G11C2213/79

    摘要： A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.

    摘要翻译： 电阻改变存储器阵列架构包括排列成行和列的电阻改变存储单元单元的阵列，其中至少两个相邻列共享一个感测位线，以及一个单独与每列相关联的控制线，其中每个中的电流控制部件 沿着相应列的单位单元耦合到相应的控制线。 该架构进一步包括多个与相应行相关联的字线，其中与相应行的每个单位单元相关联的电阻改变元件被耦合到相应的字线。

    Direct tunneling memory with separated transistor and tunnel areas
    26.
    发明授权
    Direct tunneling memory with separated transistor and tunnel areas 失效
    具有分离晶体管和隧道区域的直接隧道存储器

    公开(公告)号：US07462539B2

    公开(公告)日：2008-12-09

    申请号：US11892872

    申请日：2007-08-28

    申请人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

    发明人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

    IPC分类号： H01L21/00 ,  H01L21/20

    CPC分类号： H01L27/11526 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/0692 ,  H01L29/7883

    摘要： A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.

    摘要翻译： 半导体器件具有形成在半导体衬底上的隔离区域，并且限定包括选择晶体管区域和直接隧道元件区域的连续有源区域; 形成在所述选择晶体管区域的沟道区上的栅极绝缘膜; 隧道绝缘膜，其形成在所述直接隧道元件区域的部分区域上，并且具有与所述栅极绝缘膜的厚度不同的厚度; 形成在栅极绝缘膜和隧道绝缘膜上方的连续浮栅; 形成在所述浮栅电极的表面上的电极间绝缘膜; 通过所述电极间绝缘膜与所述浮栅相对的控制栅电极; 以及形成在选择晶体管区域的沟道区域的两侧并且不与隧道绝缘膜重叠的一对源极/漏极区域。

    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
    27.
    发明授权
    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
    具有适用于小振幅操作的输入/输出接口的半导体集成电路

    公开(公告)号：US06744300B2

    公开(公告)日：2004-06-01

    申请号：US10277707

    申请日：2002-10-23

    申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

    发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

    IPC分类号： H01J1982

    CPC分类号： H03K19/018585

    摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

    摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
    28.
    发明授权
    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
    具有适用于小振幅操作的输入/输出接口的半导体集成电路

    公开(公告)号：US06492846B1

    公开(公告)日：2002-12-10

    申请号：US09474702

    申请日：1999-12-29

    申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

    发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

    IPC分类号： H03K300

    CPC分类号： H03K19/018585

    摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

    摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过这种结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

    Bus configuration and input/output buffer
    29.
    发明授权
    Bus configuration and input/output buffer 有权
    总线配置和输入/输出缓冲器

    公开(公告)号：US06480030B1

    公开(公告)日：2002-11-12

    申请号：US09648621

    申请日：2000-08-28

    申请人： Masao Taguchi

    发明人： Masao Taguchi

    IPC分类号： H03K190175

    CPC分类号： G11C7/1057 ,  G06F13/4077 ,  G06F13/4086 ,  G11C7/1051 ,  G11C2207/2227 ,  H03K19/0016 ,  H03K19/017545 ,  H03K19/018585 ,  Y02D10/14 ,  Y02D10/151

    摘要： A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

    摘要翻译： 用于信号传输的系统具有用于信号传输的至少一个总线和设置在连接到总线的短截线上的防反射电阻，用于防止在总线和短截线之间的交叉点处的信号的反射。 该系统包括终端电阻以及用于通过第一模式中的终端电阻将总线耦合到终端电压并且用于在第二模式中将总线与终端电压断开的开关单元。

    Reference voltage generation circuit using source followers
    30.
    发明授权
    Reference voltage generation circuit using source followers 有权
    使用源跟随器的参考电压发生电路

    公开(公告)号：US06225855B1

    公开(公告)日：2001-05-01

    申请号：US09154167

    申请日：1998-09-16

    申请人： Masao Taguchi

    发明人： Masao Taguchi

    IPC分类号： G05F110

    CPC分类号： G05F3/262 ,  G11C5/147

    摘要： A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor has a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.

    摘要翻译： 参考电压产生电路包括：负载单元，其一端连接到较高电压电源线; 增强型n沟道MIS晶体管，其漏极连接到负载单元的另一端，其源极连接到较低电压电源线; 并且使用MIS晶体管的源极跟随器电路具有驱动元件，源极跟随器电路的输入端连接到n沟道MIS晶体管的漏极，并且其输出端连接到n沟道MIS的栅极 晶体管。 在n沟道MIS晶体管的漏极处获得参考电压。 通过该结构，可以获得稳定的参考电压，并且将参考电压产生电路并入到通过集成MIS晶体管而生成的集成电路中，而不引入生产过程的增加。 也可以减小参考电压产生电路的消耗电流。