公开(公告)号：US11658135B2

公开(公告)日：2023-05-23

申请号：US16747971

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Ernst Seler ,  Markus Josef Lang ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01Q1/22 ,  G01S13/08 ,  G01S13/931

CPC classification number: H01L23/66 ,  G01S13/08 ,  H01L23/49816 ,  H01L24/16 ,  H01Q1/2283 ,  G01S13/931 ,  H01L2223/6622 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2224/16225

Abstract: A semiconductor device comprises a substrate having a first surface and a second surface opposite the first surface, at least one connection element arranged on the first surface of the substrate to electrically and mechanically connect the substrate to a printed circuit board, and a radar semiconductor chip arranged on the first surface of the substrate.

公开(公告)号：US20200303815A1

公开(公告)日：2020-09-24

申请号：US16356316

申请日：2019-03-18

Applicant: Infineon Technologies AG

Inventor： Ashutosh Baheti ,  Marwa Abdel-Aziz ,  Mustafa Dogan ,  Muhammad Tayyab Qureshi ,  Saverio Trotta ,  Maciej Wojnowski

IPC: H01Q1/52 ,  H01Q9/04 ,  H01Q19/00 ,  G01S7/03 ,  G01S7/282 ,  G01S7/285 ,  G01S13/32

Abstract: A packaged radar includes laminate layers, a ground plane associated with at least one of the laminate layers, a transmit antenna and a receive antenna associated with at least one of the laminate layers, and an electromagnetic band gap structure between the transmit antenna and the receive antenna for isolating the transmit antenna and the receive antenna, the electromagnetic band gap structure including elementary cells forming adjacent columns each coupled to the ground plane, and each elementary cell including a conductive planar element and a columnar element coupled to the conductive planar element.

公开(公告)号：US20200006174A1

公开(公告)日：2020-01-02

申请号：US16447610

申请日：2019-06-20

Applicant: Infineon Technologies AG

Inventor： Christian GEISSLER ,  Walter Hartner ,  Claus Waechter ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L21/56

Abstract: A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

公开(公告)号：US20190067223A1

公开(公告)日：2019-02-28

申请号：US16173702

申请日：2018-10-29

Applicant: Infineon Technologies AG

Inventor： Rudolf Lachner ,  Linus Maurer ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01Q9/04 ,  H01L23/31 ,  H01L23/00 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/12 ,  H01L24/19 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q9/0457 ,  H01L2924/00

Abstract: A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material.

公开(公告)号：US10121751B2

公开(公告)日：2018-11-06

申请号：US15137594

申请日：2016-04-25

Applicant: Infineon Technologies AG

Inventor： Rudolf Lachner ,  Linus Maurer ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor module comprises an integrated circuit device, the IC device embedded in a compound material, wherein the compound material at least partially extends lateral to the IC device. The semiconductor module further comprises interconnect structures arranged lateral to the IC device to provide at least one external electrical contact; a patch antenna structure integrated in the semiconductor module and electrically connected to the IC device and a layer interfacing the IC device and the compound, wherein the layer comprises first and second planar metal structures coupled to the IC device, wherein the first planar metal structure is electrically connected to the IC device and the interconnect structures and wherein the second planar metal structure is electrically connected to the IC device and the patch antenna structure.

公开(公告)号：US09349696B2

公开(公告)日：2016-05-24

申请号：US14148585

申请日：2014-01-06

Applicant: Infineon Technologies AG

Inventor： Rudolf Lachner ,  Linus Maurer ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/12 ,  H01L24/19 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q9/0457 ,  H01L2924/00

Abstract: A semiconductor module comprises a wafer package comprising an integrated circuit (IC) device embedded within the wafer package and a layer comprising at least one antenna structure and redistribution structures, wherein the antenna structure is coupled to the IC device and wherein the redistribution structures are coupled to the IC device.

Abstract translation: 半导体模块包括晶片封装，其包括嵌入在晶片封装内的集成电路（IC）器件和包括至少一个天线结构和再分配结构的层，其中天线结构耦合到IC器件，并且其中再分配结构耦合 到IC设备。

公开(公告)号：US09337522B2

公开(公告)日：2016-05-10

申请号：US14067640

申请日：2013-10-30

Applicant: Infineon Technologies AG

Inventor： Saverio Trotta ,  Jagjit Singh Bal ,  Maciej Wojnowski ,  Ernst Seler ,  Mehran Pour Mousavi

IPC: H01P5/107 ,  H01P3/12 ,  H04B10/2575 ,  H04B10/572 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01P5/107 ,  H01P3/12 ,  H04B10/2575 ,  H04B10/572 ,  H05K1/0206 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/181 ,  H05K3/4697

Abstract: According to an embodiment, a circuit board includes a signal line including at least portion of a first conductive layer that has a first portion extending over a cavity in the circuit board from a first side of the cavity. The circuit board also includes a first plurality of conductive vias surrounding the cavity and the first plurality of vias include at least one blind via disposed adjacent to the first side of the cavity.

Abstract translation: 根据实施例，电路板包括信号线，该信号线包括第一导电层的至少一部分，第一导电层具有第一部分，该第一部分从空腔的第一侧延伸到电路板中的空腔上。 电路板还包括围绕空腔的第一多个导电通孔，并且第一多个通孔包括邻近空腔的第一侧设置的至少一个盲孔。

公开(公告)号：US08952521B2

公开(公告)日：2015-02-10

申请号：US13736553

申请日：2013-01-08

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Walter Hartner ,  Ottmar Geitner ,  Gottfried Beer ,  Klaus Pressel ,  Mehran Pour Mousavi

IPC: H01L23/04 ,  H01L23/66 ,  H01L21/768 ,  H01L23/498 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17519 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01Q23/00 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01064 ,  H01L2924/01044 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract translation: 在本发明的一个实施例中，半导体封装包括具有第一主表面和相对的第二主表面的衬底。 芯片设置在基板中。 芯片包括在第一主表面处的多个接触垫。 第一天线结构设置在第一主表面处。 反射器设置在第二主表面处。

公开(公告)号：US08624381B2

公开(公告)日：2014-01-07

申请号：US13849034

申请日：2013-03-22

Applicant: Infineon Technologies AG

Inventor： Rudolf Lachner ,  Linus Maurer ,  Maciej Wojnowski

IPC: H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/12 ,  H01L24/19 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q9/0457 ,  H01L2924/00

Abstract: A semiconductor module, comprises a package molding compound layer comprising an integrated circuit (IC) device embedded within a package molding compound, the integrated circuit device and the package molding compound having a common surface. Structures are formed to connect the semiconductor module to an external board, the structures electrically connected to the integrated circuit device. A layer is formed on the common surface, the layer comprising at least one integrated antenna structure, the integrated antenna structure being coupled to the IC device.

Abstract translation: 半导体模块包括封装模制化合物层，其包含嵌入封装模塑料中的集成电路（IC）器件，集成电路器件和具有共同表面的封装模塑料。 形成结构以将半导体模块连接到外部板，该结构电连接到集成电路器件。 在公共表面上形成一个层，该层包括至少一个集成天线结构，该集成天线结构耦合到该IC器件。

公开(公告)号：US11387533B2

公开(公告)日：2022-07-12

申请号：US16032589

申请日：2018-07-11

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Dirk Hammerschmidt ,  Walter Hartner ,  Johannes Lodermeyer ,  Chiara Mariotti ,  Thorsten Meyer

IPC: G02B6/12 ,  H01P3/16 ,  H01Q3/44 ,  H01L23/66

Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.