公开(公告)号：US20210050455A1

公开(公告)日：2021-02-18

申请号：US17074251

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L29/40 ,  H01L29/49

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20200083354A1

公开(公告)日：2020-03-12

申请号：US16465763

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Van H. LE ,  Benjamin CHU-KUNG ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200066515A1

公开(公告)日：2020-02-27

申请号：US16303125

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Willy RACHMADY ,  Marc C. FRENCH ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Ashish AGRAWAL

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

公开(公告)号：US20190088747A1

公开(公告)日：2019-03-21

申请号：US16198725

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Niti GOEL ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Marko RADOSAVLIJEVIC ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/20

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20180151684A1

公开(公告)日：2018-05-31

申请号：US15576253

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Scott B. CLENDENNING ,  Jack T. KAVALIEROS

IPC: H01L29/45 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

Abstract: An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：US20170236936A1

公开(公告)日：2017-08-17

申请号：US15499794

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L21/762 ,  H01L29/34 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/7624 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

公开(公告)号：US20150325481A1

公开(公告)日：2015-11-12

申请号：US14798380

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/8258 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract translation: 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够给出给定布局区域的显着的驱动电流。

公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.