公开(公告)号：US20200212075A1

公开(公告)日：2020-07-02

申请号：US16633559

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/027 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

公开(公告)号：US20200168274A1

公开(公告)日：2020-05-28

申请号：US16636904

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: G11C13/00 ,  H01L27/24

Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.

公开(公告)号：US20190006417A1

公开(公告)日：2019-01-03

申请号：US16069122

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Mark L. DOCZY ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE

IPC: H01L27/22 ,  G11C11/16

Abstract: Approaches and structures for unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bi-polar coercivity are described. In an example, a memory array includes a plurality of bitlines and a plurality of select lines. The memory array also includes a plurality of memory elements located among and coupled to the plurality of bitlines and the plurality of select lines. Each of the plurality of memory elements includes a unipolar switching magnetic tunnel junction (MTJ) device and a select device.

公开(公告)号：US20180165065A1

公开(公告)日：2018-06-14

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Justin S. BROCKMAN ,  Juan G. ALZATE VINASCO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Satyarth SURI ,  Robert S. CHAU ,  Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/02

CPC classification number: G06F7/588 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US20170200884A1

公开(公告)日：2017-07-13

申请号：US15324589

申请日：2014-08-05

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Anurag CHAUDHRY ,  Robert S. CHAU

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe configurations and techniques to increase interfacial anisotropy of magnetic tunnel junctions. In embodiments, a magnetic tunnel junction may include a cap layer, a tunnel barrier, and a magnetic layer disposed between the cap layer and the tunnel barrier. A buffer layer may, in some embodiments, be disposed between the magnetic layer and a selected one of the cap layer or the tunnel barrier. In such embodiments, the interfacial anisotropy of the buffer layer and the selected one of the cap layer or the tunnel barrier may be greater than an interfacial anisotropy of the magnetic layer and the selected one of the cap layer or the tunnel barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20160365385A1

公开(公告)日：2016-12-15

申请号：US15247710

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： Ravi PILLARISETTY ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  David L. KENCKE ,  Uday SHAH ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US20220199839A1

公开(公告)日：2022-06-23

申请号：US17133599

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab SEN GUPTA ,  Urusa ALAAN ,  Justin WEBER ,  Charles C. KUO ,  Yu-Jin CHEN ,  Kaan OGUZ ,  Matthew V. METZ ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Brian S. DOYLE ,  Van H. LE

IPC: H01L29/872 ,  H01L27/07 ,  H01L29/47 ,  H01L29/22

Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

公开(公告)号：US20220109025A1

公开(公告)日：2022-04-07

申请号：US17552546

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20200212105A1

公开(公告)日：2020-07-02

申请号：US16634109

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Brian S. DOYLE

IPC: H01L27/24 ,  H01L27/22

Abstract: Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line.

公开(公告)号：US20190378972A1

公开(公告)日：2019-12-12

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.