公开(公告)号：US10290561B2

公开(公告)日：2019-05-14

申请号：US15279222

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Omkar G. Karhade ,  Kedar Dhane ,  Chandra M. Jha

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/427 ,  H01L23/433

Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

公开(公告)号：US11776864B2

公开(公告)日：2023-10-03

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Edvin Cetegen ,  Nicholas Neal ,  Sergio Chan Arguedas

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/10152 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US11646274B2

公开(公告)日：2023-05-09

申请号：US16444615

申请日：2019-06-18

Applicant: Intel Corporation

Inventor： Mufei Yu ,  Gang Duan ,  Edvin Cetegen ,  Baris Bicen ,  Rahul Manepalli

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L24/09 ,  H01L2924/3511

Abstract: An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11551994B2

公开(公告)日：2023-01-10

申请号：US16139401

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Kelly Lofgreen ,  Chia-Pin Chiu ,  Joseph Petrini ,  Edvin Cetegen ,  Betsegaw Gebrehiwot ,  Feras Eid

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/00

Abstract: Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US11464139B2

公开(公告)日：2022-10-04

申请号：US16180499

申请日：2018-11-05

Applicant: Intel Corporation

Inventor： Kelly Lofgreen ,  Joseph Petrini ,  Todd Coons ,  Christopher Wade Ackerman ,  Edvin Cetegen ,  Yang Jiao ,  Michael Rutigliano ,  Kuang Liu

IPC: H05K7/20

Abstract: A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.

公开(公告)号：US20210391295A1

公开(公告)日：2021-12-16

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210343677A1

公开(公告)日：2021-11-04

申请号：US16862287

申请日：2020-04-29

Applicant: Intel Corporation

Inventor： Frederick W. Atadana ,  Taylor William Gaines ,  Edvin Cetegen ,  Wei Li ,  Hsin-Yu Li ,  Tony Dambrauskas

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29

Abstract: Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

公开(公告)号：US20210249322A1

公开(公告)日：2021-08-12

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.