公开(公告)号：US10122265B1

公开(公告)日：2018-11-06

申请号：US15861604

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： George E. Matthew ,  Gerhard Schrom ,  Alexander Lyakhov ,  Rachid E. Rayess ,  Anant S. Deval ,  Sergio Carlo Rodriguez ,  Pushkar Dixit

IPC: H02M1/44 ,  H02M3/157 ,  H01F27/40

Abstract: An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a mid-point of the at least two switches and an output terminal; a first circuitry to compare a current through the inductor with a threshold current, and to control one or both of the at least two switches, based at least in part on the comparison; and a second circuitry to randomly vary the threshold current over consecutive cycles of switching of the at least two switches.

公开(公告)号：US08994344B2

公开(公告)日：2015-03-31

申请号：US13727227

申请日：2012-12-26

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  Peter Hazucha ,  Jaeseo Lee ,  Tanay Karnik ,  Vivek K. De ,  Fabrice Paillet

IPC: G05F1/46 ,  H02M1/14 ,  H02M7/06

CPC classification number: G05F1/468 ,  H02M1/14 ,  H02M7/068

Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.

公开(公告)号：US10374614B2

公开(公告)日：2019-08-06

申请号：US15854624

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  Sarath Makala ,  Kowshik Gandham ,  Chun Lee

IPC: G06F1/12 ,  H03L7/00 ,  H03L7/085 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal, a memory element to store the values of the output information, a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information, and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element.

公开(公告)号：US10354786B2

公开(公告)日：2019-07-16

申请号：US15283350

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Gerhard Schrom ,  Edward A. Burton

IPC: H01L23/64 ,  H01F1/147 ,  H01F10/06 ,  H01F27/255 ,  H01F27/28 ,  H01F41/04 ,  H01F41/16 ,  H01F41/32 ,  H01L25/18 ,  H01L49/02 ,  H05K3/00 ,  H01F17/00 ,  H01F27/36 ,  H05K1/16 ,  H01F41/26 ,  H01F41/18

Abstract: Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic particles, wherein the magnetic particles are suspended in an insulating medium.

公开(公告)号：US20190199358A1

公开(公告)日：2019-06-27

申请号：US15854624

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  Sarath Makala ,  Kowshik Gandham ,  Chun Lee

IPC: H03L7/085 ,  H03L7/099 ,  G06F1/08

CPC classification number: H03L7/00 ,  G06F1/12 ,  H03L7/085 ,  H03L7/0991

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal, a memory element to store the values of the output information, a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information, and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element.

公开(公告)号：US09696350B2

公开(公告)日：2017-07-04

申请号：US13907802

申请日：2013-05-31

Applicant: INTEL CORPORATION

Inventor： Edward A. Burton ,  Gerhard Schrom ,  Michael W. Rogers ,  Alexander Lyakhov ,  Ravi Sankar Vunnam ,  Jonathan P. Douglas ,  Fabrice Paillet ,  J. Keith Hodgson ,  William Dawson Kesling ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan ,  Samie Samaan ,  George Geannopoulos

IPC: H02M3/157 ,  G01R19/00 ,  H03L5/00 ,  H03M1/66 ,  G06T3/40 ,  H02M3/156 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

CPC classification number: G01R19/0092 ,  G06T3/40 ,  H02M1/088 ,  H02M3/156 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0009 ,  H02M2003/1566 ,  H03L5/00 ,  H03M1/66 ,  H03M1/685

Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

公开(公告)号：US20160170456A9

公开(公告)日：2016-06-16

申请号：US13626357

申请日：2012-09-25

Applicant: INTEL CORPORATION

Inventor： Siva G. Narendra ,  James W. Tschanz ,  Howard A. Wilson ,  Donald S. Gardner ,  Peter Hazucha ,  Gerhard Schrom ,  Tanay Karnik ,  Nitin Borkar ,  Vivek K. De ,  Shekhar Y. Borkar

IPC: G06F1/26 ,  G06F1/32 ,  H01L25/065

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  H01L23/34 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract translation: 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。