公开(公告)号：US20240105576A1

公开(公告)日：2024-03-28

申请号：US17953210

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Kyle MCELHINNY ,  Xiaoying GUO ,  Hiroki TANAKA ,  Haobo CHEN

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core and a pad over the core. In an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. In an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.

公开(公告)号：US20240105575A1

公开(公告)日：2024-03-28

申请号：US17953206

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jason M. GAMBA ,  Haifa HARIRI ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Kyle MCELHINNY ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Haobo CHEN ,  Bai NIE ,  Numair AHMED

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

公开(公告)号：US20220285278A1

公开(公告)日：2022-09-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Oscar OJEDA ,  Arnab ROY ,  Vahidreza PARICHEHREH ,  Leonel R. ARANA ,  Chung Kwang TAN ,  Robert A. MAY

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20220223527A1

公开(公告)日：2022-07-14

申请号：US17712944

申请日：2022-04-04

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20220199515A1

公开(公告)日：2022-06-23

申请号：US17690964

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20250089156A1

公开(公告)日：2025-03-13

申请号：US18367963

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Mohamed R. SABER ,  Manohar KONCHADY ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Hiroki TANAKA ,  Gang DUAN

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include an apparatus with a glass core and a via. In an embodiment, the apparatus comprises a layer, where the layer is a solid layer of glass. An opening is provided through the layer, and a via is in the opening. The via comprises a first material, where the first material comprises at least one metallic element, and a second material, where the second material comprises carbon.

公开(公告)号：US20240355751A1

公开(公告)日：2024-10-24

申请号：US18136722

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Sanjay THARMARAJAH ,  Hiroki TANAKA ,  Clayton BRENNER

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L21/4846

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a substrate and a pad on the substrate. In an embodiment, a layer is over the pad and the substrate, and an opening through the layer is above the pad. In an embodiment, sidewalls of the layer define the opening. In an embodiment, an undercut at an end of the opening adjacent to the pad is provided, where the undercut is positioned between the pad and the layer. In an embodiment, a bump is in the opening, where the bump at least partially fills the undercut

公开(公告)号：US20240178145A1

公开(公告)日：2024-05-30

申请号：US18434347

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20240088121A1

公开(公告)日：2024-03-14

申请号：US18511641

申请日：2023-11-16

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.