公开(公告)号：US08933458B2

公开(公告)日：2015-01-13

申请号：US14048923

申请日：2013-10-08

Applicant: Intel Corporation

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/10 ,  H01L29/76 ,  H01L29/04 ,  H01L21/306 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 描述了半导体膜的图案化方法。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US12009433B2

公开(公告)日：2024-06-11

申请号：US16001837

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Van H. Le ,  Inanc Meric ,  Gilbert Dewey ,  Sean Ma ,  Abhishek A. Sharma ,  Miriam Reshotko ,  Shriram Shivaraman ,  Kent Millard ,  Matthew V. Metz ,  Wilhelm Melitz ,  Benjamin Chu-Kung ,  Jack Kavalieros

IPC: H01L29/786 ,  H01L21/28 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78678 ,  H01L21/28194 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/7869

Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

公开(公告)号：US11996404B2

公开(公告)日：2024-05-28

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1033 ,  H01L2221/68363

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11812600B2

公开(公告)日：2023-11-07

申请号：US16452099

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Charles C. Kuo ,  Abhishek A. Sharma ,  Van H. Le ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B12/05 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  H10B12/036 ,  H10B12/33 ,  H10B12/482

Abstract: An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.

公开(公告)号：US20230352598A1

公开(公告)日：2023-11-02

申请号：US18345641

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Kent Millard ,  Jack Kavalieros ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Justin R. Weber ,  Tahir Ghani ,  Li Huey Tan ,  Kevin Lin

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/267

Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

公开(公告)号：US11784251B2

公开(公告)日：2023-10-10

申请号：US16457752

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Gilbert Dewey ,  Abhishek Sharma ,  Van H. Le ,  Jack Kavalieros

IPC: H01L29/78 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/78391 ,  H01L29/6684 ,  H10B61/00 ,  H10B63/00

Abstract: A transistor includes a semiconductor body including a material such as an amorphous or polycrystalline material, for example and a gate stack on a first portion of the body. The gate stack includes a gate dielectric on the body, and a gate electrode on the gate dielectric. The transistor further includes a first metallization structure on a second portion of the body and a third metallization structure on a third portion of the body, opposite to the second portion. The transistor further includes a ferroelectric material on at least a fourth portion of the body, where the ferroelectric material is between the gate stack and the first or second metallization structure.

公开(公告)号：US20230317558A1

公开(公告)日：2023-10-05

申请号：US17711848

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Wilfred Gomes ,  Anand Murthy ,  Tahir Ghani ,  Jack Kavalieros ,  Rajabali Koduri

IPC: H01L23/473 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L23/473 ,  H01L29/42392 ,  H01L29/0673

Abstract: Integrated circuit dies, systems, and techniques are described related to multiple transistor epitaxial layer source and drain transistor circuits operable at low temperatures. A system includes an integrated circuit die having a number of transistors each having a crystalline channel structure, a first layer epitaxial to the channel structure, and a second layer epitaxial to the first layer. The system further includes a cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

公开(公告)号：US11616130B2

公开(公告)日：2023-03-28

申请号：US16363632

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

公开(公告)号：US11532601B2

公开(公告)日：2022-12-20

申请号：US16386200

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L25/07 ,  H01L29/78 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/088 ,  H01L25/00 ,  H01L29/423 ,  H01L29/20

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

公开(公告)号：US11316027B2

公开(公告)日：2022-04-26

申请号：US16833375

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Nazila Haratipour ,  Tanay Gosavi ,  I-Cheng Tung ,  Seung Hoon Sung ,  Ian Young ,  Jack Kavalieros ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/24 ,  H01L29/92

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.