公开(公告)号：US09299400B2

公开(公告)日：2016-03-29

申请号：US13631781

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4078

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4078

Abstract: A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 存储器控制器响应于分布式检测器的检测器发出目标刷新命令。 存储器装置包括检测逻辑，该检测逻辑监视行敲击事件，该行敲击事件是对时间阈值内可能导致数据损坏到物理相邻行（“受害者”行）的行的阈值数量。 存储器件向存储器控制器发送行锤事件的指示。 响应于行锤事件指示，存储器控制器将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US11010304B2

公开(公告)日：2021-05-18

申请号：US15865642

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  John B. Halbert

IPC: G11C29/00 ,  H04L1/00 ,  G06F12/0879 ,  G06F3/06 ,  G06F12/02 ,  G11C11/16 ,  G11C11/408 ,  G06F11/10 ,  G06F12/0846 ,  G11C7/10 ,  G06F12/0893 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/409 ,  G11C29/42 ,  G06F12/06

Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.

公开(公告)号：US10242727B2

公开(公告)日：2019-03-26

申请号：US15983009

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/409 ,  G11C7/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US10210925B2

公开(公告)日：2019-02-19

申请号：US15835050

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

IPC: G06F12/00 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US20180137005A1

公开(公告)日：2018-05-17

申请号：US15814336

申请日：2017-11-15

Applicant: Intel Corporation

Inventor： Wei Wu ,  Uksong Kang ,  Hussein Alameer ,  Rajat Agarwal ,  Kjersten E. Criss ,  John B. Halbert

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/108 ,  G11C5/063 ,  G11C7/10 ,  G11C11/40618 ,  G11C11/4093 ,  G11C29/44 ,  G11C29/52 ,  G11C29/835 ,  G11C29/846

Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.

公开(公告)号：US09904591B2

公开(公告)日：2018-02-27

申请号：US14918428

申请日：2015-10-20

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains ,  Debaleena Das ,  Bill Nale

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F13/00 ,  G06F11/08

CPC classification number: G06F11/1004 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F13/00

Abstract: Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.

公开(公告)号：US09704563B2

公开(公告)日：2017-07-11

申请号：US14940073

申请日：2015-11-12

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

公开(公告)号：US20170060680A1

公开(公告)日：2017-03-02

申请号：US14998059

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

Abstract translation: 检查位读取模式使存储器件能够向关联的主机提供内部校验位。 存储器子系统的存储器控​​制器可以为存储器子系统的存储器件生成一个或多个读取命令。 读取命令可以包括地址位置信息。 存储器件包括具有可与地址位置信息寻址的存储器位置的存储器阵列。 存储器位置具有相关联的数据和内部校验位，其中校验位由存储器内部产生用于纠错。 如果存储器设备被配置为检查位读取模式，则响应于读取命令，它发送与所识别的地址位置相关联的内部校验位。 如果存储器件未配置检查位读取模式，则它将响应于读取命令返回数据，而不暴露内部校验位。

公开(公告)号：US20160254044A1

公开(公告)日：2016-09-01

申请号：US14865754

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Nadav Bonen ,  Tomer Levy

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract translation: 存储器子系统刷新管理使得命令能够使用单个命令访问跨不同银行组的一个或多个识别的银行。 每个银行组分别单独发送在单独的银行组中发送标识银行或银行的命令，该命令可以导致存储设备访问不同银行组中的银行。 该命令可以是刷新命令。 该命令可以是预充电命令。

公开(公告)号：US09361970B2

公开(公告)日：2016-06-07

申请号：US14327127

申请日：2014-07-09

Applicant: INTEL CORPORATION

Inventor： Andre Schaefer ,  John B. Halbert

IPC: G11C8/00 ,  G11C11/4074 ,  G11C8/14 ,  G11C11/408 ,  G11C8/08 ,  G11C11/404 ,  G06F1/32

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4045 ,  G11C11/4085 ,  Y02D10/14

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Abstract translation: 公开的实施例可以包括具有能够选择性地禁用多个段字线驱动器中的一个的逻辑的段字线的装置。 逻辑可以划分设备的页面，以通过激活段数字段线路中的禁用的一个来减少消耗的功率。 可以公开其他实施例。