公开(公告)号：US12048165B2

公开(公告)日：2024-07-23

申请号：US16914140

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H10B53/00 ,  G11C11/22 ,  H01G4/008 ,  H01L27/08 ,  H01L49/02 ,  H10B53/10

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01G4/008 ,  H01L27/0805 ,  H01L28/65 ,  H10B53/10

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US20240114695A1

公开(公告)日：2024-04-04

申请号：US17957560

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Christopher Neumann ,  Shriram Shivaraman ,  Brian Doyle ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. A capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. The cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.

公开(公告)号：US20240114693A1

公开(公告)日：2024-04-04

申请号：US17958202

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher M. Neumann ,  Brian Doyle ,  Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Uygar E. Avci ,  Eungnak Han ,  Manish Chandhok ,  Nafees Aminul Kabir ,  Gurpreet Singh

IPC: H01L27/11514 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11504

CPC classification number: H01L27/11514 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11504

Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.

公开(公告)号：US20240105854A1

公开(公告)日：2024-03-28

申请号：US18528545

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US20240006494A1

公开(公告)日：2024-01-04

申请号：US17856206

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656

Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.

公开(公告)号：US11721735B2

公开(公告)日：2023-08-08

申请号：US17580550

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Van H. Le ,  Abhishek A. Sharma ,  Tahir Ghani ,  Willy Rachmady ,  Rishabh Mehandru ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Shriram Shivaraman

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/66545

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US11522060B2

公开(公告)日：2022-12-06

申请号：US16142036

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Justin Weber ,  Matthew Metz ,  Arnab Sen Gupta ,  Abhishek Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Charles Kuo ,  Nazila Haratipour ,  Shriram Shivaraman ,  Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Sean Ma

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  H01L27/108 ,  H01L21/02 ,  H01L29/267 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11450750B2

公开(公告)日：2022-09-20

申请号：US16146654

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Van H. Le ,  Shriram Shivaraman ,  Abhishek Sharma

IPC: H01L23/532 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/10 ,  H01L27/105

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20210398993A1

公开(公告)日：2021-12-23

申请号：US16906217

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC: H01L27/11507 ,  H01L23/522 ,  H01L21/768

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

公开(公告)号：US11171243B2

公开(公告)日：2021-11-09

申请号：US16455581

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L29/221 ,  H01L21/8238 ,  H01L27/092

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.