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公开(公告)号：US11018871B2
公开(公告)日：2021-05-25
申请号：US15941407
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Kapil Sood , Naveen Lakkakula , Hari K. Tadepalli , Lokpraveen Mosur , Rajesh Gadiyar , Patrick Fleming
Abstract: A security accelerator device stores a first credential that is uniquely associated with the individual security accelerator device and represents a root of trust to a trusted entity. The device establishes a cryptographic trust relationship with a client entity that is based on the root of trust, the cryptographic trust relationship being represented by a second credential. The device receives and store a secret credential of the client entity, which is received via communication secured by the second credential. Further, the device executes a cryptographic computation using the secret client credential on behalf of the client entity to produce a computation result.
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公开(公告)号：US20210117191A1
公开(公告)日：2021-04-22
申请号：US17133305
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Andrew Cunningham , Patrick Fleming , Naveen Lakkakula , Richard Guerin , Charitra Sankar , Stephen Doyle , Ralph Castro , John Browne
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.
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公开(公告)号：US20190104022A1
公开(公告)日：2019-04-04
申请号：US15721373
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Damien Power , Patrick Fleming , Michael J. McGrath , Jonathan Kenny , David Hunt
Abstract: A data center orchestrator, including: a hardware platform; a host fabric interface to communicatively couple the orchestrator to a network; an orchestrator engine to provide a data center orchestration function; and a data structure, including a network function virtualization definition (NFVD) instance, the NFVD instance including a definition for instantiating a virtual network function (VNF) on a host platform, including a telemetry fingerprint policy description (TFPD) for the VNF, wherein the TFPD includes information to collect telemetry data selected from a set of available telemetry data for the host platform.
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公开(公告)号：US20190050347A1
公开(公告)日：2019-02-14
申请号：US16045393
申请日：2018-07-25
Applicant: Intel Corporation
Inventor： Anatoli Bolotov , Mikhail Grinchuk , David M. Durham , Patrick Fleming
Abstract: Systems, apparatus, and/or methods to provide memory data protection. In one example, authenticated encryption may be enhanced via a modification to an authentication code that is associated with encrypted data. The authentication code may be modified, for example, with a nonce value generated for a particular write to memory Decrypted data, generated from the encrypted data, may then be validated based on a modified authentication code. Moreover, data freshness control for data stored in the memory may be provided based on iterative authentication and re-encryption. In addition, a counter used to provide a nonce value may be managed to reduce a size of the counter and/or a growth of the counter.
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公开(公告)号：US20190044879A1
公开(公告)日：2019-02-07
申请号：US16023743
申请日：2018-06-29
Applicant: Intel Corporation
Inventor： Bruce Richardson , Andrew Cunningham , Alexander J. Leckey , Brendan Ryan , Patrick Fleming , Patrick Connor , David Hunt , Andrey Chilikin , Chris MacNamara
IPC: H04L12/863 , H04L12/935 , H04L12/861 , H04L12/801
Abstract: Technologies for reordering network packets on egress include a network interface controller (NIC) configured to associate a received network packet with a descriptor, generate a sequence identifier for the received network packet, and insert the generated sequence identifier into the associated descriptor. The NIC is further configured to determine whether the received network packet is to be transmitted from a compute device associated with the NIC to another compute device and insert, in response to a determination that the received network packet is to be transmitted to the another compute device, the descriptor into a transmission queue of descriptors. Additionally, the NIC is configured to transmit the network packet based on position of the descriptor in the transmission queue of descriptors based on the generated sequence identifier. Other embodiments are described herein.
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Patent Agency Ranking
公开(公告)号：US20190044860A1
公开(公告)日：2019-02-07
申请号：US16011103
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Chris MacNamara , John Browne , Tomasz Kantecki , Ciara Loftus , John Barry , Patrick Connor , Patrick Fleming
IPC: H04L12/801 , H04L12/861 , H04L12/841
Abstract: Technologies for providing adaptive polling of packet queues include a compute device. The compute device includes a network interface controller and a compute engine that includes a set of cores and a memory that includes a queue to store packets received by the network interface controller. The compute engine is configured to determine a predicted time period for the queue to receive packets without overflowing, execute, during the time period and with a core that is assigned to periodically poll the queue for packets, a workload, and poll, with the assigned core, the queue to remove the packets from the queue. Other embodiments are also described and claimed.
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公开(公告)号：US12026116B2
公开(公告)日：2024-07-02
申请号：US17134361
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Patrick G. Kutch , Andrey Chilikin , Niall D. McDonnell , Brian A. Keating , Naveen Lakkakula , Ilango S. Ganga , Venkidesh Krishna Iyer , Patrick Fleming , Lokpraveen Mosur
IPC: G06F13/40 , G06F3/06 , G06F9/50 , G06F12/0802 , G06F13/42
CPC classification number: G06F13/4027 , G06F3/0604 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F9/5083 , G06F12/0802 , G06F13/4221 , G06F2212/6042 , G06F2213/0026 , G06F2213/40
Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
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公开(公告)号：US20240128982A1
公开(公告)日：2024-04-18
申请号：US18397651
申请日：2023-12-27
Applicant: Intel Corporation
Inventor： Smita Kumar , Patrick Fleming
CPC classification number: H03M7/3068 , H03M7/3048
Abstract: A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
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公开(公告)号：US20230412459A1
公开(公告)日：2023-12-21
申请号：US18241609
申请日：2023-09-01
Applicant: Intel Corporation
Inventor： Ciara Loftus , Chris MacNamara , John J. Browne , Patrick Fleming , Tomasz Kantecki , John BARRY , Patrick Connor
IPC: H04L41/0896 , H04L47/762 , H04L47/70 , G06F11/34 , H04L41/5019 , H04L49/00 , H04L41/0816
CPC classification number: H04L41/0896 , H04L47/762 , H04L47/822 , G06F11/3442 , H04L41/5019 , H04L49/70 , H04L41/0816
Abstract: Technologies for dynamically selecting resources for virtual switching include a computing device configured to identify a present demand on processing resources of the computing device that are configured to process data associated with network packets received by the computing device. Additionally, the computing device is configured to determine a present capacity of one or more acceleration resources of the computing device and configure the virtual switch based on the present demand and the present capacity of the acceleration resources. Other embodiments are described herein.
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公开(公告)号：US11431351B2
公开(公告)日：2022-08-30
申请号：US16297577
申请日：2019-03-08
Applicant: Intel Corporation
Inventor： David K. Cassetti , Stephen T. Palermo , Sailesh Bissessur , Patrick Fleming , Lokpraveen Mosur , Smita Kumar , Pradnyesh S. Gudadhe , Naveen Lakkakula , Brian Will , Atul Kwatra
IPC: H03M7/34 , H03M7/30 , H03M7/40 , G06F40/126 , G06F40/149 , G06F40/157 , G06F40/284 , H03M7/00 , H03M5/00 , H03M7/42
Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.
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