公开(公告)号：US20250107112A1

公开(公告)日：2025-03-27

申请号：US18371294

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas PIETAMBARAM ,  Mohammad Mamunur RAHMAN ,  Sashi Shekhar KANDANUR ,  Aleksandar ALEKSOV ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI

IPC: H01L23/48 ,  H01L23/498

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

公开(公告)号：US20250038114A1

公开(公告)日：2025-01-30

申请号：US18918478

申请日：2024-10-17

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US20240213156A1

公开(公告)日：2024-06-27

申请号：US18089491

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Tarek A. IBRAHIM ,  Aaron GARELICK ,  Srikant NEKKANTY ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/53209 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/642 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/04026 ,  H01L2224/05567 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29101 ,  H01L2924/1436 ,  H01L2924/15321

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

公开(公告)号：US20240088121A1

公开(公告)日：2024-03-14

申请号：US18511641

申请日：2023-11-16

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20240063069A1

公开(公告)日：2024-02-22

申请号：US17892930

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Rahul N. MANEPALLI ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/15

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/15 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.

公开(公告)号：US20240006297A1

公开(公告)日：2024-01-04

申请号：US17853582

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Darko GRUJICIC ,  Marcel WALL ,  Yi YANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L23/538 ,  H01L21/481

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006283A1

公开(公告)日：2024-01-04

申请号：US17853487

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattawa NAD ,  Rahul N. MANEPALLI ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Yi YANG ,  Marcel WALL ,  Darko GRUJICIC ,  Haobo CHEN ,  Aaron GARELICK

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.

公开(公告)号：US20230420375A1

公开(公告)日：2023-12-28

申请号：US18367285

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/09 ,  H01L25/0652

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20230317584A1

公开(公告)日：2023-10-05

申请号：US17707371

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Suddhasattwa NAD ,  Marcel WALL ,  Rahul N. MANEPALLI ,  Benjamin DUONG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/181 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon and nitrogen, and wherein the second layer is chemically bonded to one of the first layers by an oxygen containing ligand and/or a nitrogen containing ligand.