公开(公告)号：US20170323962A1

公开(公告)日：2017-11-09

申请号：US15525164

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  HAROLD W. KENNEL ,  GLENN A. GLASS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

公开(公告)号：US20170221724A1

公开(公告)日：2017-08-03

申请号：US15489569

申请日：2017-04-17

Applicant: INTEL CORPORATION

Inventor： ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  RAVI PILLARISETTY ,  NILOY MUKHERJEE ,  JACK T. KAVALIEROS ,  ROZA KOTLYAR ,  WILLY RACHMADY ,  MARK Y. LIU

IPC: H01L21/3215 ,  H01L29/06 ,  H01L29/778 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

公开(公告)号：US20170125524A1

公开(公告)日：2017-05-04

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20200381549A1

公开(公告)日：2020-12-03

申请号：US16998382

申请日：2020-08-20

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20200007135A1

公开(公告)日：2020-01-02

申请号：US16024052

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： ABHISHEK A. SHARMA ,  RAVI PILLARISETTY ,  CHARLES KUO ,  WILLY RACHMADY

IPC: H03M1/00 ,  H03M1/74

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

公开(公告)号：US20200006340A1

公开(公告)日：2020-01-02

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  ANH PHAN ,  GILBERT DEWEY ,  WILLY RACHMADY ,  STEPHEN M. CEA ,  SAYED HASAN ,  KERRYANN M. FOLEY ,  PATRICK MORROW ,  COLIN D. LANDON ,  EHREN MANNEBACH

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：US20200006329A1

公开(公告)日：2020-01-02

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  CHENG-YING HUANG ,  CHRISTOPHER JEZEWSKI ,  EHREN MANNEBACH ,  RISHABH MEHANDRU ,  PATRICK MORROW ,  ANAND S. MURTHY ,  ANH PHAN ,  WILLY RACHMADY

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L23/00

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US20190088759A1

公开(公告)日：2019-03-21

申请号：US16080824

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7856

Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

公开(公告)号：US20180358440A1

公开(公告)日：2018-12-13

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

公开(公告)号：US20160365416A1

公开(公告)日：2016-12-15

申请号：US15120803

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  WILLY RACHMADY ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  RAVI PILLARISETTY ,  ROBERT S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract translation: 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 本文还包括其它实施例。