公开(公告)号：US20210036026A1

公开(公告)日：2021-02-04

申请号：US17072850

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20200335582A1

公开(公告)日：2020-10-22

申请号：US16918952

申请日：2020-07-01

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/8605 ,  H01L27/098

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US20200266194A1

公开(公告)日：2020-08-20

申请号：US16347183

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Rohan K. BAMBERY ,  Walid M. HAFEZ ,  Mong-Kai WU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/525

Abstract: Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.

公开(公告)号：US20190237564A1

公开(公告)日：2019-08-01

申请号：US16344003

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66 ,  H01L29/66356 ,  H01L29/66818 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：US20180226432A1

公开(公告)日：2018-08-09

申请号：US15946666

申请日：2018-04-05

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/84

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20160111426A1

公开(公告)日：2016-04-21

申请号：US14977367

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851 ,  H01L29/7855

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Abstract translation: 描述了具有不同栅极结构并形成在单个集成电路上的两种或多种类型的鳍式晶体管。 每种类型的晶体管的栅极结构至少区别于栅极电介质层的厚度或组成或栅电极中功函数金属层的组成。 还提供了用于制造具有至少两种不同类型的基于鳍的晶体管的集成电路的方法，其中晶体管类型通过栅极电介质层的厚度和组成和/或工件的厚度和组成来区分 功能金属在栅电极。

公开(公告)号：US20240145477A1

公开(公告)日：2024-05-02

申请号：US18410917

申请日：2024-01-11

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

公开(公告)号：US20240113128A1

公开(公告)日：2024-04-04

申请号：US18538795

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20230299087A1

公开(公告)日：2023-09-21

申请号：US18140931

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/66484 ,  H01L29/408 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/40114 ,  H01L21/823456 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/7831 ,  H01L29/517

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US20220077302A1

公开(公告)日：2022-03-10

申请号：US17526986

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.