公开(公告)号：US20200051915A1

公开(公告)日：2020-02-13

申请号：US16474589

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Sai Boyapati ,  Wei-Lun Kane Jen ,  Javier Soto Gonzalez

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/48 ,  H01L23/495 ,  H01L21/768 ,  H01L23/532

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.

公开(公告)号：US09788416B2

公开(公告)日：2017-10-10

申请号：US14778987

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： Wei-Lun Kane Jen ,  Padam Jain ,  Dilan Seneviratne ,  Chi-Mon Chen

IPC: H01L23/13 ,  H05K1/02 ,  H01L21/02 ,  H01L23/12 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H01L25/065 ,  H05K1/03

CPC classification number: H05K1/0271 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/0044 ,  H05K2201/0191 ,  H05K2201/05 ,  H05K2203/0278 ,  H05K2203/085 ,  H01L2924/00

Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

公开(公告)号：US20160133552A1

公开(公告)日：2016-05-12

申请号：US14992535

申请日：2016-01-11

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。

公开(公告)号：US09236366B2

公开(公告)日：2016-01-12

申请号：US13722203

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stephanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H05K3/40 ,  H01L25/065 ,  H01L23/14 ,  H01L23/538 ,  H05K1/03 ,  H05K1/14 ,  H05K3/46 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。