公开(公告)号：US11937514B2

公开(公告)日：2024-03-19

申请号：US17313403

申请日：2021-05-06

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Daniel Charles Edelstein ,  Chih-Chao Yang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10B63/00 ,  H10N70/011 ,  H10N70/231 ,  H10N70/841

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

公开(公告)号：US20220359814A1

公开(公告)日：2022-11-10

申请号：US17313403

申请日：2021-05-06

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Daniel Charles Edelstein ,  Chih-Chao Yang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

公开(公告)号：US20200350486A1

公开(公告)日：2020-11-05

申请号：US16401206

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.

公开(公告)号：US09536780B1

公开(公告)日：2017-01-03

申请号：US15130814

申请日：2016-04-15

Applicant: International Business Machines Corporation

Inventor： Chih-chao Yang ,  Daniel Charles Edelstein

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  C23C16/45544 ,  C23C16/50 ,  H01L21/3212 ,  H01L21/67098 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/1087

Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.

Abstract translation: 本公开涉及使用单个室进行多次处理，导致具有互连的半导体芯片。 许多示例性方法包括形成通孔以暴露微芯片的多个层。 这些层可以包括图案化介电层，封盖层，第一金属层和绝缘体。 然后实施表面改性步骤以修饰和/或致密化电介质表面的经处理的表面。 然后执行金属化合物去除步骤以从通孔的底部除去金属化合物。 最后，通孔填充导电材料。 表面改性和金属化合物去除步骤在一个室中实现。

公开(公告)号：US20240162087A1

公开(公告)日：2024-05-16

申请号：US17985138

申请日：2022-11-10

Applicant: International Business Machines Corporation

Inventor： Xiaoming Yang ,  Yann Mignot ,  SOMNATH GHOSH ,  Daniel Charles Edelstein

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L21/76877 ,  H01L21/0272 ,  H01L21/0332 ,  H01L21/76802

Abstract: A semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity.

公开(公告)号：US11955152B2

公开(公告)日：2024-04-09

申请号：US17541401

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

公开(公告)号：US20240006316A1

公开(公告)日：2024-01-04

申请号：US17854444

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Christian Lavoie ,  Daniel Charles Edelstein ,  Ruilong Xie

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L29/78696 ,  H01L21/76898 ,  H01L27/0924 ,  H01L21/823871

Abstract: Semiconductor devices, and methods of their formation, are provided. The semiconductor device can include a substrate; a wiring level within the substrate; and at least one buried power rail within the wiring level, wherein the at least one buried power rail is divided into a plurality of rail segments, wherein each rail segment of the plurality of rail segments has a length smaller than a total length of the buried power rail.

公开(公告)号：US20230189655A1

公开(公告)日：2023-06-15

申请号：US17548828

申请日：2021-12-13

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Lisamarie White ,  Willie Lester Muchrison, JR. ,  Scott A. DeVries ,  Daniel Charles Edelstein ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) structure that includes a memory element a non-sacrificial hardmask stack over the memory element. The non-sacrificial hardmask stack includes a first hardmask region and a second hardmask region. A compressive stress level of the first hardmask region is greater than a compressive stress level of the second hardmask region.

公开(公告)号：US20230178129A1

公开(公告)日：2023-06-08

申请号：US17541401

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

CPC classification number: G11C11/161 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L27/222

Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

公开(公告)号：US20230165155A1

公开(公告)日：2023-05-25

申请号：US17530690

申请日：2021-11-19

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Daniel Charles Edelstein ,  Andrew Giannetta

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L27/222

Abstract: A method of manufacturing a double magnetic tunnel junction device includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, forming a metallic ring layer on the sides of the spin conducting layer; and forming a second magnetic tunnel junction stack on the spin conducting layer. The second magnetic tunnel junction stack has a width that is greater than the width of the first magnetic tunnel junction stack. A double magnetic tunnel junction device includes a first magnetic tunnel junction stack, a spin conducting layer on the first magnetic tunnel junction stack, a metallic ring layer on the sides of the spin conducting layer; and a second magnetic tunnel junction stack on the spin conducting layer. The second magnetic tunnel junction stack has a width that is greater than the width of the first magnetic tunnel junction stack.